# Current mirror design - gate to drain feedback

In my texbook [Analog VLSI: Circuits and Principles] there are two circuits that function as a current mirror. The first uses two nfets with a shared gate, and the drain of the first nfet (M1) is tied to the common gate. The current through M1 is then mirrored through M2.

The book also shows a Winner Take All circuit that uses a current mirror where the gate of M2 is tied to the drain of M1. And the gate of M1 is tied to the source of M2.

The book states "We should remember that Vg is determined by the gate charge, which cannot be directly influenced by the input current due to the infinite impedance between channel and gate." For the second current mirror design, how is the current getting mirrored to M2 if the gate can not be directly set by the input current in M1?

simulate this circuit – Schematic created using CircuitLab

This is most succinctly explained in Carver Mead's 1989 book on neuromorphic engineering, Analog VLSI and neural systems. In the two circuits above, the top one is a current mirror and the bottom one a current conveyor. The both assume saturation of the devices. In the current conveyor, the assumption is that the voltage across M1 is larger than $4U_t$ for saturation. Firstly, you also need to "untie" the bulk from the source of M2 and M1 and not assume that the source is tied to GND. You then can setup the two current equations for the devices.

• ps: I'd give you more but this is very much like homework that I've assigned in the past, so I only wanted to get you started. – b degnan Jan 8 '17 at 18:09