# Does anyone know how to build asynchronous mod 10 down counter using t flip flops?

I know how to build asynchronous down counter , but it starts with F and ends at 0 and a need it to start at 9 and count to 0.The T flip flop has a set and reset and i need to use them so that it can count form 9 to 0.If anyone has any idea that would be helpful.

• because that is the assignment... sadly Jan 8, 2017 at 17:18
• adding the homework tag, in that case. Jan 8, 2017 at 17:31
• But: you'll need to show a bit of own attempt, explain what you've tried, what you've got stuck with. Like it is now, we can't tell where to start or stop explaining. Jan 8, 2017 at 17:32
• Does it need to count from 9 to 0 repeatedly, or do you provide an external signal to reset it to 9? First, figure out how to wire the set and reset lines to set the flip flops to 9. Then, figure out what gates can detect when it should reset. Jan 8, 2017 at 17:33
• yes it need to count from 9 to 0 repeatedly, well since the counter starts with F i tried when the value of the counter is 1111(F) to reset the counter , same when its 0000 (0) , but it doesn't work , also tried to reset only the second and third TFF when the value is 1111 ( so the value from 1111 changes to 1001 which is actually 9 and continues to count) but that also doesn't work Jan 8, 2017 at 17:46

## Up counter from 0-9

Assume we have 4-bit async. counter that counts up from 0 -> 15

One way to limit this counter would be to simulate the 1111 bit patteren whenever the current output is equal to 9

In other words, whenver the output is equal to 9 1001 we need to toggle OUT[3] and not to toggle OUT[1] the next clock cycle so we end up with a 0000

Assuming this is our T flip-flop model in verilog

module TFF (CLK,T,OUT);
input CLK,T;
output reg OUT=0;
always @ ( posedge CLK ) begin
if(T) OUT<=~OUT;
else  OUT<=OUT;
end
endmodule // TFF


And we have built some combinatorial logic circuit that checks the counter output if its equal to 9 it will make sure to toggle OUT[3] and to not toggle OUT[1] the next clock cycle

module NINE_YET (IN,OUT);
input  [3:0] IN;
output reg [1:0]OUT;
always @ ( * ) begin
if(IN==9) OUT<=2'b01; //Q[3] should be toggled the next cycle, Q[2] should not
else OUT<={~IN[2],~IN[0]}; //just pass Q of Tff[2] and Tff[0]
end
endmodule // NINE_YET


And this is the top module where everything is connected

module TOP (CLK,OUT);
input CLK;
output [3:0] OUT;
wire [1:0]nine_yet_op;
NINE_YET m(OUT,nine_yet_op);

TFF Q0(CLK,1'b1,OUT[0]);
TFF Q1(nine_yet_op[0],1'b1,OUT[1]);
TFF Q2(~OUT[1],1'b1,OUT[2]);
TFF Q3(nine_yet_op[1],1'b1,OUT[3]);
endmodule // TOP


This is the same connection as the count-up counter that counts from 0 -> 15 but the only difference is that the CLK inputs of the 4th and 2nd flip flops are connected to the combinatorial circuit that checks if the output is 9 or not

And this is the result

I don't know why initially the flip flops output is set to 1111 i think im missing something in my testbench, but i hope you got the idea

• Build a normal down-counter
• Start inserting some combinatorial circuit that toggle the correct flip flop[s] the next cycle once the required bit pattern is detected
• i don't how to make the T flip flops to go from 1111 directly to 1001 and then continue to count to 0 when i reset the flip flops from 1111 goes directly to 0000 Jan 8, 2017 at 18:16
• Well assuming each flipflop initial value is zero would make more sense in this case your logic will handle who should be triggered the next cycle and who should not ending up with the first and the last flip flops being triggered with the pattern 1001. But in case they are initially all set to 1 you need extra clock cycle to store the required bit pattern inside them and then they will count down till zero at this point your logic will handle who to trigger next and so on Jan 8, 2017 at 18:20

Assuming you have an up counter 0->15.

IIRC, if you take the outputs from the !Q's instead of Q's you get a 15-0 down counter.

Then, you can build logic that when the count is zero will force the necessary T's such that the next step is 9 instead of 15 (on the !Q's outputs).

As input for that logic, you have available 4 Q's and 4 !Q's (just use the ones you need). Design the 0->9 logic in any way you know (e.g. Karnaugh map).