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I'm trying to detect the phase difference between two signals (voltage and current) given from the same source (an ultrasound generator) which works at 20kHz approximately.

I found a circuit that is supposed to do that, but when I do the simulation with LTSpice I think that I'm doing it wrong because it does not works as it's told in the page. I think that the D-Flip Flop is not working as expected.

I "test it" using different phases for one of the signals and it gives me very different results in the different simulations.

Can anyone look at the file and give me some help so I can do the simulation correctly?

I attach the LTSpice file:

https://www.dropbox.com/sh/be6k6jhx6h9ipo5/AACywKL40KTgJz2wyFPXie0sa?dl=1

Image obtained from: www.next.gr/meter-counter/meters/measuring-phase-difference-l12144.html

image obtained from: www.next.gr/meter-counter/meters/measuring-phase-difference-l12144.html

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  • \$\begingroup\$ Looks good to me (D F/F output is high when A leads B, low when B leads A). In what way is it not working 'as expected'? \$\endgroup\$ – Bruce Abbott Jan 8 '17 at 19:58
  • \$\begingroup\$ Thank you for your quick answer. I think it's not working as the page which I obtain the photo says it works (www.next.gr/meter-counter/meters/measuring-phase-difference-l12144.html). I should get different dc values if I get different phase shifts, or not? \$\endgroup\$ – Augusto Bonelli Toro Jan 8 '17 at 20:07
  • \$\begingroup\$ Your LtSpice file does not simulate the entire circuit. \$\endgroup\$ – Steve G Jan 8 '17 at 20:49
  • \$\begingroup\$ Oh, DB didn't synchronize the file. Sorry. Here is the complete circuit dropbox.com/sh/be6k6jhx6h9ipo5/AACywKL40KTgJz2wyFPXie0sa?dl=1 \$\endgroup\$ – Augusto Bonelli Toro Jan 8 '17 at 21:41
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The D flip-flop is working as expected, but your simulation has other issues:-

  1. the LT1716 comparator is much slower than the uA710 (~3us switching time vs 20ns). At 20kHz this slow switching causes noticeable pulse timing distortion. To improve accuracy you need to lower the input frequency (to eg. 2kHz).

  2. Your digital logic blocks are set at their default logic levels of 0-1V (compared to ~0-3.5V for TTL) so the output amplitude will be lower than in the original circuit.

Note that the uA710 has TTL compatible outputs, but with a negative supply the LT1716 will pull below ground (which is not compatible with most digital logic families). It only works in LTspice because the simulated logic has no input voltage restrictions.

Other issues are shared with the original circuit:-

  1. No resistor between the flop-flop output and 2N2369 Base. In a real circuit this would probably stress the flip-flop and increase saturation voltage of the transistor.

  2. The 2N2369 has a fairly high saturation voltage which affects the output when it is turned on. It should be replaced with a low saturation type such as FTZ849.

  3. When the transistor turns on it reconfigures the associated op amp from inverting to non-inverting mode, but also lowers the impedance at point E which reduces the signal voltage. This can be fixed by inserting a unity gain buffer amp between the output of the low pass filter and the 2x 15k resistors.

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  • \$\begingroup\$ Oh, thank you for the observations, I'm doing the changes right now! I don't understand how to make the digital blocks to have a range from 0v to 3.5v. Can you enlight me? \$\endgroup\$ – Augusto Bonelli Toro Jan 9 '17 at 12:28
  • \$\begingroup\$ Right-click on the component to edit its attributes, double-click in the value column of the "Value" attribute and enter "Vhigh=3.5". \$\endgroup\$ – Bruce Abbott Jan 9 '17 at 17:24
  • \$\begingroup\$ Hi! I changed the circuit following your recomendations (except the transistor because the soft doesn't have it) and change the flip-flop source for a positive one instead the -5v. I think that the circuit isn't working as the web tolds it works. Can you look it please? Thank very very much for your help \$\endgroup\$ – Augusto Bonelli Toro Jan 10 '17 at 0:54
  • \$\begingroup\$ link to your latest version? \$\endgroup\$ – Bruce Abbott Jan 10 '17 at 2:40
  • \$\begingroup\$ It's the same, I uploaded the DB file! dropbox.com/sh/be6k6jhx6h9ipo5/AACywKL40KTgJz2wyFPXie0sa?dl=1 \$\endgroup\$ – Augusto Bonelli Toro Jan 10 '17 at 2:46

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