# How can pipelining hurt the clock frequency?

As I understand it, pipelining is used to speed up the clock frequency by processing more instructions at once, and longer pipelines should improve the clock frequency. However, my instructor mentioned that in some cases pipelining could actually hurt the clock, particularly when splitting on the memory stage. I'm having trouble envisioning how this is possible-- surely it could hurt the CPI due to hazards, but it seems like the clock frequency should be unaffected. Can somebody point out to me what I'm missing?

• Doesn't he mean that pushing the pipeline makes more important the delay of registers compared with the actual processing time? – clabacchio Mar 13 '12 at 11:05

Other problem that may arise is the junction of pipeline and branch prediction. The prediction tries to guess which is the more probable result from an if instruction and starts to evaluate the guessed path from code even before the result is known. All these instructions are therefore pipelined through the processor. If the guess appears to be wrong, the processor must wait until the pipeline buffer to clear before starting to evaluate the correct path.