0
\$\begingroup\$

I am somewhat confused with why someone would want to buffer a CMOS logic gate and what the advantages are to doing so. Let's say I have a certain CMOS logic gate such as a NAND gate as shown below:

enter image description here

This is fairly simple to understand in terms of logic and input voltage levels. You would call this CMOS NAND gate "unbuffered". What I want to understand is if you add two NOT gates to the output of this circuit, you would still have the same CMOS NAND gate but it would be considered "buffered". Could someone explain me what are the advantages of adding additional NOT gates at the output of a logic block and how do they buffer your output?

The circuit I am asking about would look like this:

schematic

simulate this circuit – Schematic created using CircuitLab

\$\endgroup\$
  • \$\begingroup\$ Have you seen this application note "Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics" by TI? Located here ti.com/lit/an/scha004/scha004.pdf. \$\endgroup\$ – Tyler Jan 9 '17 at 16:40
4
\$\begingroup\$

It's to do with providing stable and predicable output drive characteristics for a CMOS logic device.

Read TI's document on the subject

Buffered CMOS
A buffered CMOS device is one for which the output ON impedance is independent of any and all valid input logic conditions, both preceding and present, and is said to have a buffered output or to be a buffered CMOS device.

\$\endgroup\$
3
\$\begingroup\$

In your NAND gate above what is the output path when one input is high and one is low? Now what is the output path when both inputs are low?

In both situations the output is high. But with one low the output is driven through a single P channel. When both are low the output is driven through two P channel devices in parallel.

This means that the current driving characteristics of the output are dependent not just on the logical value of the output but also on the combination of inputs used to generate that output. Hardly the ideal situation for a logic gate.

By buffering the output through a couple of not gates the output characteristics become independent of the individual input pin states and depend purely on the logical output value.

\$\endgroup\$
1
\$\begingroup\$

It comes down to the RC constant. If you have a big cap at the output, you would want a low Ron of the preceding circuit to charge it fast enough and get a 'good' output. If you directly connect a NAND gate to output, if your input is slewed with a slow slope, the Ron of the NAND will be very high and take a while to charge the output cap. But if you put NOT gates then your last stage input is purely digital which will charge/discharge your output cap very fast.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.