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How does having more or less capacitance at the output of a DC/DC buck converter contribute to the location of the poles and zeros. Is there a way to crudely make this calculation.

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  • 1
    \$\begingroup\$ See: ti.com/lit/an/slva301/slva301.pdf \$\endgroup\$ – winny Jan 9 '17 at 22:37
  • \$\begingroup\$ The overall output L and C of a buck will have a gain peak at their resonant frequency and a roll-off beyond that point. Part of a well-designed feedback loop is verification of stability at both the specified minimum and maximum output capacitance. \$\endgroup\$ – Adam Lawrence Jun 12 '17 at 2:22
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It depends on many factors. The load (ohmic or others), the state variables, the operation mode (CCM/DCM) and others. After you decide these factors you can formulate the state matrices (A,B,C,D).

Following is a simple Matlab code may help you studying any converter poles position with different capacitor values. The state formulation is taken from this paper. The capacitor varies between \$5 \mu F\$ and \$50 \mu F\$ with step change of \$5 \mu F\$.

L=1e-3;  
R=10;    
c=5e-6;   
d=0.5;
B=[d/L;0];
C=[1 0;0 1];
D=[0;0];
hold on
for i=1:10
    A=[0 -1/L;1/c -1/(R*c)];  
    sys=idss(A,B,C,D);
    pzmap(sys);
    c=c+5e-6;
end

And the result for this particular case,

enter image description here

So for this particular formulation, the increment of capacitor drag the poles of the system to the right hand side of the poles map.

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  • \$\begingroup\$ Where is ESR in your analysis? What practical value is it without component limitations? of ESR in e-caps and DCR in chokes and Ron in switches. \$\endgroup\$ – Sunnyskyguy EE75 Jan 26 '18 at 20:19
  • \$\begingroup\$ As I mentioned in the answer, this is a general code to analyse pole placement of any converter. If the user is interested in including ESR or any other practical element, he/she may modify (A,B,C,D) accordingly and run the code. \$\endgroup\$ – Hazem Jan 27 '18 at 3:27
  • \$\begingroup\$ My point is without ESR included any analysis is invalid. \$\endgroup\$ – Sunnyskyguy EE75 Jan 27 '18 at 9:19
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The output capacitance causes a pole. However, how relevant this is to stability depends a great deal on the control algorithm. For example, a pulse on demand system doesn't have a stability issue in the first place, although it can go meta-stable, and the output capacitor and its ESR can affect that.

Before you talk about stability, you have to describe the control algorithm you are using. Different algorithms have different inherent poles and zeros.

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    \$\begingroup\$ "Pulse on demand" = hysteretic? \$\endgroup\$ – M D Jan 10 '17 at 9:13
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If you look at the output filter of buck converter it is a simple LC low pass network with a resistive load. It has a bode plot like this: -

enter image description here

As you can see there is a peak in the frequency response at about 16 kHz and this is due to the Q of the circuit.

The Q for this type of circuit is \$R\sqrt{\frac{C}{L}}\$.

With the values I've chosen, Q = 100 and produces a 100x peak at resonance. That's +40 dB on the graph. If I were to increase the capacitance by 100 times Q would become 1000. If I decreased Q by 100 times, Q would be 10.

Next is to understand that a change of Q means a movement of pole position. However, to make a calculation of pole-position it is more useful to use the term "damping ratio" (or \$\zeta\$) instead of Q where \$\zeta\$ = 1/2Q.

So as Q rises, \$\zeta\$ falls. Now take a look at these two pictures below (left and right): -

enter image description here

On the left is a 3D view of the pole-zero diagram and this is for a low pass 2nd order filter exactly like the LC filter on a buck converter. In other words, it is relevant to the question.

In the 3D picture you should be able to see is the bode plot view and how it fits into the bigger picture of the pole zero diagram. On the right is the traditional pole-zero digram i.e. it is looking from above down onto the 3D picture on the left.

One pole is shown for convenience (although there are two symmetrical poles) and its position is determined by only two parameters: \$\omega_n\$ and \$\zeta\$.

  • Real part is \$-\omega_n\zeta\$
  • Imaginery part is \$\omega_n\sqrt{1-\zeta^2}\$

However those co-ordinates can be divided by \$\omega_n\$ leaving just \$\zeta\$ as the factor that moves the pole position.

So, if \$\zeta\$ is very small (i.e. the Q is very high and the bode plot peak is correspondingly high) the pole position is much closer to the jw axis. This can cause instability and certainly a lot of transient ringing on the output of a buck converter.

To add a little more meat, if you return to the original bode plot and look at the phase response of the filter you will see that at DC there is no phase lag or lead and this remains largely so until you hit the resonance of the filter. At resonance the phase response inverts to 180 degrees pretty rapidly. So, if this filter is within the control loop of the buck regulator, you need to take additional measures to prevent negative feedback turning into positive feedback at resonance and above.

How does having more or less capacitance at the output of a DC/DC buck converter contribute to the location of the poles and zeros. Is there a way to crudely make this calculation.

  1. Estimate the load resistance from output voltage and current
  2. Plug values into Q formula
  3. Convert Q to zeta
  4. \$\zeta\$ tells you how close the pole is to the jw axis

If the output capacitor has significant ESR I would want to make a simulation because of the effect it has on the phase response, For instance, here's the same values as used in the original bode plot but with 0.05 ohms in series with C1: -

enter image description here

Now the phase angle doesn't quite reach -180 degrees and therefore some margin of stability has been achieved. However, this will be at the expense of a very slight increase in switching ripple. But remember, in any (if not all) buck converters some form of lead compensation is done in the error amplifier to "pull" the overall phase response significantly away from -180 degrees and back towards higher stability; it doesn't matter that this is a switching converter - you could model it as a linear amplifier with the output filter LC within the feedback loop - without that lead compensation the buck converter will be unstable because it sails just too close to having open loop gain at phase angles close to -180 degrees.

The position of the poles caused by the LC filter are now affected by lead compensation and what might of been a crude way to predict their position becomes less accurate and some form of simulation is what I would recommend.

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  • \$\begingroup\$ that's a nice and heavily invested question. Thank you. Unfortunately we all are too busy to just experiment with some buck EVK and see what happens... \$\endgroup\$ – Gregory Kornblum Jan 26 '18 at 8:51
  • \$\begingroup\$ Analysis looks excellent but neglects ESR which affects results greatly. for 10uF e-cap , ESR*C=T ranges from 7us to 500us and Zo=1 ohm so Q will be substantially lower than 100 and as shown will be <2. \$\endgroup\$ – Sunnyskyguy EE75 Jan 26 '18 at 20:11
  • \$\begingroup\$ The last part covers ESR @TONY. BTW I worked on Mc phereson street for a while. I'm positive you'll know where. \$\endgroup\$ – Andy aka Jan 26 '18 at 23:35
  • \$\begingroup\$ give me a clue.. \$\endgroup\$ – Sunnyskyguy EE75 Jan 27 '18 at 1:34
  • \$\begingroup\$ @tony dunno if still there but they made metal detectors, called goring kerr and more latterly thermo. \$\endgroup\$ – Andy aka Jan 27 '18 at 8:26
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The output capacitance has a non-linear effect on the regulation. Remember that the buck converter can provide current to drive the output capacitor voltage in the positive direction only. If the voltage is instantaneously too high from a rapid change in load, inductive kick, or an increase in line voltage, the capacitor can only be discharged through the load current and not by the converter. So you have different ramp times for charging and discharging the cap, and if your load is varying, the discharge time will vary with it. You can choose the output cap large enough for reduction in noise and ripple, but if you make the cap too large, the power supply will recover only slowly from overshoot. In general if you keep the time constant of the output capacitance and minimum load short enough (don't run unloaded), the output capacitance will not dominate. Similarly, your inductor max current will only charge the capacitor so fast. So the "crude" answer is to use the smallest output capacitor consistent with your required ripple current and then make sure your loop time constant is timed to make the cap response irrelevant as @Olin Lathrop says above. It is not a good idea to make the power supply response time constant dependent on the output capacitor, because variation in the load changes its contribution.

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The question is erroneous, because it assumes falsely that the value of Cout is the only contributing factor to stability when it depends on DCM,CCM mode , loop compensation, Cap ESR*C=T values and more directly, chip design if it is internally compensated, which is better for simple design in the feedback loop.

All e-caps have at least one breakpoint defined by the series ESR or Rs and associated capacitance, C such that T=ESR*C. The design and quality of such caps has a wide range of T values where ultra-low ESR is T < 10us and general purpose e-caps are T > 100us and ceramic/plastic caps have T<< 1us. Remember that 1/T=ω.

Keep in mind a bigger cap also means bigger ESR in the same family and thus more ripple which also gives more feedback without as much phase shift so it is also more stable but more ripple on the output. Then adding smaller caps in parallel reduces the high frequency ripple but at the expense of reducing phase margin which shows up as step load overshoot.

Therefore , although C value has a significant effect on the ripple and stability of the loop, more important is the understanding that it is the ESR*C values of all capacitors for stability and also the choice of internally compensation IC's or not and choice of external loop compensation.

In Op Amp design , unity gain loop stability is possible with internal compensation because we only consider small signal response here, meaning no current limited slew rate. But in a SMPS, each pulse is ramping up towards full current on a pulse to pulse basis with PWM cutoff so the ESR of your switch, inductor and load capacitor as well as load resistance ratios are all interactive in the feedback loop stability of this control system for poles and zeros, unlike simple Op Amps. So it is much more complex.

See excellent example below which has low ripple 25mΩ//5mΩ//100uΩ due ultra low ESR from 2 e-caps and 50x ceramic caps all in parallel , yet 60 deg phase margin!
enter image description here

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Reading in IEEE Transactions on Circuits and Systems (the Yellow rag), some years ago the hot topic was Switching Regulators and the Stability thereof.

Problem with switchers is the LARGE # of poles and zeros, as parasitics and silicon sneak paths get modeled.

I recall the # being 8 or 10 or 13 poles+zeros.

And this other perilous problem: Consider the feedback loop inside some silicon chip, with 1mm * 1mm loop area, being 1mm away from some aggressor magnetic field that may be inside the chip or just outside. What voltage gets induced in this, from 1 amp/1nanosecond current transient?

Using a combination of Biot-Savart and Faraday, written for long straight wire coupling into a loop coplanar with the wire, we have the useful formula

Vinduce = 2e-7 * Area/Distance * dI/dT

In a 1mm cube model of Area/Distance, we get 2e-7H/m * 0.001m * 10^+9 amp/sec, or

Vinduce = 2e-10 * 1e-9 == 2e-1 == 0.2 volts. Can you have a reliable SwitchReg with 0.2 volt spikes injected into the feedback circuits? I think not.

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  • \$\begingroup\$ So what's the conclusion? \$\endgroup\$ – Gregory Kornblum Feb 5 '17 at 5:20
  • \$\begingroup\$ OP asks for the effect of output cap when used more or less than calculated. \$\endgroup\$ – Rohat Kılıç Feb 5 '17 at 5:37
  • \$\begingroup\$ The OP asked a "stability" question. I've explained (1) the model needs to include the higher order parasitics; (2) the model needs to include magnetically-induced feedback, not just the intended voltage-divider feedback. \$\endgroup\$ – analogsystemsrf Feb 16 '17 at 5:14
  • \$\begingroup\$ Where do you have 1 amp/nanosecond transients? \$\endgroup\$ – immibis Jan 23 '18 at 0:02

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