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Curious if there is a general rule for optimizing total resistance values in a voltage divider reference in a comparator circuit. Guessing it ultimately comes down to whether maximizing accuracy or minimizing power is a bigger concern.

For instance, the LMV331 (http://www.digikey.com/product-detail/en/stmicroelectronics/LMV331ICT/497-10355-2-ND/2217242) gives a max input bias current of 400 nA:

LMV331 datasheet

Assume VDD = 5 V, my process would be to take Ibias*100 = 40 uA. 5 V / 40 uA = 125 kΩ (total resistance). Then set up R1 + R2 as needed to get the desired voltage reference. This would give ~1% accuracy at a power consumption of 5 * 5 / 125k = 0.2 mW.

So, if we wanted to compare against a 1V reference, the resulting circuit would look like:

schematic

simulate this circuit – Schematic created using CircuitLab

Is this a good overall approach?

Edit: changed reference to 1V per Tony's correction.

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  • \$\begingroup\$ The undefined input to your question is, what are your limits for power budget, total equivalent input voltage offset ( or error tolerance) and temperature range? and also SNR/noise bandwidth \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 9 '17 at 23:27
  • \$\begingroup\$ Thanks Tony... In this case I was looking for a general approach as it isn't for a specific problem I am facing. But those are all good points, and things I'll remember when I have to apply it to an actual design task. \$\endgroup\$ – Jim Jan 10 '17 at 14:35
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There are several problems with your method:

  1. If you're using 1% resistors, then you probably want that error to dominate. That means the offset voltage due to the reference voltage impedance should be significantly less. I'd probably aim for no more than 20% or maybe 10% of the 1% error of the resistors. If you have four sources of error and each is 1%, then you end up with 4% overall. You probably want to avoid that.

  2. You are using the input bias current spec. If you match the impedances of the two inputs, then you can use input offset current spec.

  3. Note the rather large 7 or 9 mV (depending on your temperature range) offset voltage. This is in addition to whatever offset is caused by the offset or bias current times the impedance. No matter what tolerance resistors or other parts you use, it's not worth trying to reduce the error by a few 100 µV when the offset voltage than adds 7 mV.

  4. If you really care about comparison voltage accuracy at this level, then this is the wrong part to use. 7 mV is very large by today's standards. Modern CMOS opamps also have much lower input bias currents.

    Since you're using a 5 V supply, take a look at the MCP602x, for example. You can get parts with only 250 µV offset at 25°C, and 2.5 mV over the full extended temperature range. The max input bias current is only 150 pA up to 85°C, more than three orders of magnitude better than the part you show.

  5. The output impedance of a voltage divider is the parallel combination of the two resistors, not their sum as you seem to think. You wanted 125 kΩ output impedance, then used 100 kΩ and 25 kΩ resistors. The output impedance of that divider is actually 20 kΩ. To get the 125 kΩ you were aiming for, use 625 kΩ and 156 kΩ.

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  • \$\begingroup\$ (cont'd) Very good information. Given this isn't for any specific design task (right now) I think #1, 2, and 5 provide the most value to me. The 5V & LMV331 were chosen to give some concrete values for calculations. \$\endgroup\$ – Jim Jan 10 '17 at 14:42
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2V ref would use R2=50k, R1=75k, yes this ok approach but Vin+ input must also have Req series impedance to match Vin- to minimize Iin creating an offset voltage due to resistance mismatch.

You must compute IinReq(-)=InReq(+) then compare with Iio input offset and Vio for room temp and temp range desired. then compare with power drain and choose another if it does not meet your approval.

After you define T range['C] and that you want to use worst case not nominal, then you calculate Req for the divider (R1//R2) and lookup Iin (max over temp) and compare with Vio internal offset (typ,max) and try not exceed your error budget.

The best approach is clearly define your limits to threshold detection error , need for hysteresis, and truly define your application needs and power budget for this circuit.

It is ok to iterate these requirements as one of many tradeoffs. But it is not ok to be vague about requirements then the design cannot be verified ( by anyone) as this part of every good design practice, to have "design specs" then a test plan to verify each and every part of the design or a DVT Plan with appropriate environment tests.

  • e.g. 15~35'C V threshold 2V +/-50mV with 10mV hysteresis.) for 5V +/-1% , other sources of error are R tolerance, Iin, Iio, Vio, Rin (mismatch)

    • thus Vref is affected by 5V with 20mV error from 1% as part of overall error budget.
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  • \$\begingroup\$ Math is hard. Should have double checked the reference voltage calculation. Very good point regarding clearly defining requirements. Thanks. \$\endgroup\$ – Jim Jan 10 '17 at 14:45
  • \$\begingroup\$ 1/Req =1/R1 + 1/R2 for R1//R2 then for ratios R1/(R1+R2)*100= % of Vcc \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 10 '17 at 16:34
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The capacitance on the Vref node is useful, because that C predicts the TOTAL INTEGRATED NOISE. A fast comparator will response to all that noise. A slow comparator might not.

Using Vnoise = sqrt( K*T/C), given 10pF for C, the total noise is 20 microVolts RMS. Or, at 6 sigma (6 times RMS) to capture most of the peak-peak risk, the voltage is 20*6 = 120microVolts.

Why is this interesting? YOU get to set the bandwidth on that Vref noise, by selecting resistors, and optionally adding an additional capacitor to GND

A total cap of 100*10pF reduces the noise 10:1 (the sqrt) to 12microvoltsPP.

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