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In my undergrads, I was taught 8051 and in interrupts my professor had said that on interrupt SP points to the address that is hardcoded and Program goes to excute those instructions. But in between two address space is only where I can write interrupt handling code and I wrote more than than byte available it will overwrite the next interrupt instructions.

Now when I look at Atmega or LPC2148 Datasheet it has interrupt vector address and I am assuming that it points to a address where instructions for interrupt handling instructions are written( not exactly on those addresses). Is my assumptions correct?

P.S Due to being on low bandwidth net, I am not able to provide links to Datasheet. Would do that when I get back.

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  • \$\begingroup\$ I believe your assumption is correct \$\endgroup\$ – Matthew Jan 10 '17 at 12:55
  • \$\begingroup\$ In your sentence "SP points to ..." You probably meant "PC", right? \$\endgroup\$ – dim lost faith in SE Jan 10 '17 at 12:59
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    \$\begingroup\$ each CPU architecture may not be the same. At least Three different methods exist. Ssome use a hard-coded PC address, others use a 1 byte or 2 byte etc jump table or ISR lookup table or a dynamic jump address. ISR., IRQ documentation defines which is used. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 10 '17 at 13:20
  • \$\begingroup\$ @dim Doesn't stack pointer point to the address that is going to be loaded into PC? \$\endgroup\$ – MaNyYaCk Jan 10 '17 at 14:00
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    \$\begingroup\$ @MaNyYaCk No, the stack pointer (SP) is the address where the general-purpose register values are pushed to/popped from. It is unrelated to the program counter (PC), which indicates the address of the next instruction to be fetched. \$\endgroup\$ – dim lost faith in SE Jan 10 '17 at 14:03
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The Interrupt Service Routine (ISR) is the program that's to be executed when an interrupt occurs.

Some CPU architectures have fixed addresses which the CPU will execute a subroutine call to. This is true of the MCS-51 (8051). The ISR must start at this address. It is not uncommon to just put a Jump instruction at this address that takes the CPU to the rest of the ISR elsewhere in memory.

Other CPU architectures use interrupt vectors. The vector is a memory location at which the address of the ISR can be found. The location of the vector is known to the CPU, either by being fixed or in conjunction with a special CPU/hardware register. When the CPU services the interrupt, it reads a vector value from memory and executes a subroutine call to the vector value. This is true of the ARM, 6502 and 68000 family. External hardware may have a hand in specifying the particular vector to use within a table of vectors but the principle still stands.

So the handling of interrupts in the 8051 CPU and in the ARM CPU seem different to you because they use fundamentally different schemes for finding the address of the ISR. But these two methods (hard-coded address versus vector in memory) are pretty-much the only schemes you'll come across in all the CPUs you'll see.

(There's the occassional oddity, like the Z80 in Interrupt Mode 0 where it expects to read an instruction from external hardware that'll take it to the ISR, but I wouldn't muddy your water with that stuff while you're getting the hang of it all.)

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Interrupt vectors are the addresses on the MCU from where the interrupt service routine's address would be loaded to Program counter on occurrence of a specified/intended event. For example, the timer counter's overflow can cause an interrupt if its configured for that. If there is an interrupt service routine (ISR) associated with that timer module, the same would be called just like any normal task switching (except few exemptions).

Your understanding is partially correct, When interrupt occurs, the current execution status is backed up into the stack pointer and the program counter is loaded with the ISR's address which is basically stored in the interrupt vector address.

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The program address for an interrupt vector is the program address the CPU jumps to when an interrupt is triggered. It's just like other program addresses. In the case of AVR, adjacent ones only differ by 1 instruction, which means you can only put 1 instruction for each interrupt vector if you want to use all of them. Usually, it will be a rjmp instruction to the rest of the program that handles the interrupt.

If you use a high level language like C, you can tell the compiler to put the program in charge of handling the interrupt in the right place. Here's how: http://www.nongnu.org/avr-libc/user-manual/group__avr__interrupts.html

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  • \$\begingroup\$ What stumps me in this case is AVR documentation clearly states that "Note that the Status Register is not automatically stored when entering an interrupt routine, and it is not restored when returning from an interrupt routine. This must be handled by the application program. " Hence I need to store Status , Jump to where the ISR is, restore the status back and RETI? How does it do all that in one instruction? \$\endgroup\$ – MaNyYaCk Jan 10 '17 at 13:56
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    \$\begingroup\$ "How does it do all that in one instruction?" - it doesn't. You must manually save and restore the Status, and since that involves reading and writing an I/O location you need to save and restore at least one other register (unless you dedicate it to ISR use only). This requires several instructions, so the only useful instruction you can put at the vector address is a jump (unless subsequent vectors are not used, then you can let the code overrun them). \$\endgroup\$ – Bruce Abbott Jan 10 '17 at 18:02

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