The Interrupt Service Routine (ISR) is the program that's to be executed when an interrupt occurs.
Some CPU architectures have fixed addresses which the CPU will execute a subroutine call to. This is true of the MCS-51 (8051). The ISR must start at this address. It is not uncommon to just put a Jump instruction at this address that takes the CPU to the rest of the ISR elsewhere in memory.
Other CPU architectures use interrupt vectors. The vector is a memory location at which the address of the ISR can be found. The location of the vector is known to the CPU, either by being fixed or in conjunction with a special CPU/hardware register. When the CPU services the interrupt, it reads a vector value from memory and executes a subroutine call to the vector value. This is true of the ARM, 6502 and 68000 family. External hardware may have a hand in specifying the particular vector to use within a table of vectors but the principle still stands.
So the handling of interrupts in the 8051 CPU and in the ARM CPU seem different to you because they use fundamentally different schemes for finding the address of the ISR. But these two methods (hard-coded address versus vector in memory) are pretty-much the only schemes you'll come across in all the CPUs you'll see.
(There's the occassional oddity, like the Z80 in Interrupt Mode 0 where it expects to read an instruction from external hardware that'll take it to the ISR, but I wouldn't muddy your water with that stuff while you're getting the hang of it all.)