# schematic and algorithm for auto-range voltmeter

I'm creating Digital Voltmeter on ATmega16 with autorange to purpose. I just have a problem with designing autorange. Does anyone have a schematic of a voltage divider, and an algorithm for how auto-range should work?

I heard about FET selectable resistor ladder but currently I don't know how use it in my project. I mean schematic and how to control it from microcontroller.

The Voltmeter should be very simple - it is a project for my studies, therefore I don't want to use any digital potentiometers or sophisticated circuits. The ranges may be 2 levels for example.

• The algorithm is trivial. But if you don't even know how to design a voltage divider or how to use a FET as a switch, why did you decide to do this project?
– CL.
Commented Jan 11, 2017 at 9:40
• I know how to create simple voltage resistor divider and how does FET work. But in that project it can't be a simple resistor ladder therefore I asked that question. I just heard about fet voltage divider but how does it work exactly? Commented Jan 11, 2017 at 9:47
• @CL, the project will involve learning something new, that's the sole purpose of it. Why would anyone do a study project based on what they already know? Commented Jan 11, 2017 at 9:51
• @M_K Stack Exchange is specifically NOT about spoonfeeding people canned homework and project answers. You have Google/Instructables/forums for that. Here you will get MUCH high quality help if you put in due effort yourself. This is a superb resource for people prepared to help themselves. Not a good one for people who want premade answers. Commented Jan 11, 2017 at 10:33
• @M_K Note that if you want to measure a reference value (like 5V or 12V), it's good practice to have a measurement range where the expected value is about 80% of the maximum. You'd want to have ranges of e.g. 0-6V and 0-15V, respectively. Commented Jan 11, 2017 at 12:21

A resistor ladder with FET switches is typically used to implement an analog-to-digital converter. For example, this is from patent US3755807:

However, the ATmega16 already has an ADC, so you don't need to use such a resistor ladder.

The easiest way to handle two ranges is to use two voltage dividers, and to use two different ADC inputs on your microcontroller for them (so the switching is done by software):

If you want to save the last bit of power and to increase the input impedance a little, put FET switches between the lower resistors and ground so that you can prevent current from flowing through any unused dividers. (Or simply use GPIO pins that you can switch between ground (output zero) and high impedance (input).)

• Wouldn't one of the ADC inputs receive out-of-range signal (possibly damaging the MCU) when the higher range signal is present? Commented Jan 11, 2017 at 10:28
• Ok @CL, thanks a lot for answering. So I assume that FETs, in this case, are to ensure proper impendance but NOT to switch ranges? Instead, switching ranges is doing in software by means internal adc's mux, among another channels? Isn't it? Commented Jan 11, 2017 at 10:28
• @DmitryGrigoryev Yes; if the input can go higher, this needs clamping on the ADC inputs.
– CL.
Commented Jan 11, 2017 at 11:22

Here's one simple way:

simulate this circuit – Schematic created using CircuitLab

• When you drive D1, D2 and D3 to Z-state, there will be no voltage divider and you will be able to measure V_IN voltage in range from 0 to AREF

• When you drive D3 low, you'll get 1:1 voltage divider, and you will be able to measure V_IN voltage in range from 0 to 2*AREF

• In a similar way, driving D2 and D1 low will give you 3:1 and 7:1 dividers and measurement ranges of 4*AREF and 8*AREF respectively.

Algorithmically, you should keep driving D1 low when you connect the probe to V_IN, and progressively decrease divider ratio until the measured value increases to above 50% of your ADC range.

Shameless plug: I have a small project of mine which aims to be simple and educational, and I think I'll implement this auto-range feature next time I touch it.

Digital programmable gain using a CD4066: -

The "switches" inside the CD4066 are basically mosfets acting as either "on" or "off".

Digital programmable gain using MOSFETs: -

A mosfet as shown above can be simply presumed to be either open-circuit or short-circuit (just like a relay contact or switch). With the three mosfets open circuit, the gain is -(R2+R3)/R1. With one mosfet selected (by applying a proper gate voltage level), the feedback is reduced and the gain increases. You can choose values for Ra1, Ra2 and Ra3 to produce gains that change like this: -

Information taken from here (Digitally Programmable Amplifier Meets Sensor Gain, Ranging Needs).

• Being duly aware of the need to ensure that excessive voltage does not turn up in fatally bad ways under all conditions. Commented Jan 11, 2017 at 10:36

Create a normal voltage divider that connects between the + and - terminals of your meter inputs.

The MCU measures the output of the divider with an A/D converter.

Normally a simple voltage divider consists of an upper and lower divider resistor. To make a multi-range divider, instead of using a single resistor on the lower side use several resistors in parallel. Put a MOSFET switch between each low-side resistor and ground. By turing on different combinations of MOSFETs you can select the divider ratio.

The IO/pin on most MCUs contain an ESD diode. The ESD diode will protect the IO pin from over-voltage provided the current is limited. It is usually permissible to conduct a small ammount of DC current into the diode (the amount will be specified in the datasheet). As long as your upper divider resistor is large enough to limit the current the MCU will not be damaged.

• Noting that the ESD diode is allowed to conduct to protect the device but not in norml operation. So in this design, when not operating it may conduct but must never do so on any pin when the unit is operating (if valid uC operation is desired). Commented Jan 11, 2017 at 20:59
• @RussellMcMahon Many microcontrollers and FPGAs (Xilinx for sure) allow conduction into the ESD diode even during normal operation provided that the current is limited. I am not sure however in the case of his specific MCU. Commented Jan 11, 2017 at 21:34
• I do not know if FPGSa have especially addessed this issue BUT while many people assert that it is OK to have "some" substrate diode current in normal operation, this is amost never supported by data ssheets (which do however usually refere to absolute maximum conditions where operation is not guaranteed). I have had this "discussion" many times over the years and the situations where it is acceptable based on hard data can mostly be counted on the fingers of one hoof. | Rather than go into the reasons again again again pse refer to my answers cited below + the related ... Commented Jan 12, 2017 at 0:21
• ... questions. | Digital Input Clamp Circuit Protection and this highly relevant one and this and this Commented Jan 12, 2017 at 0:25
• @RussellMcMahon Yes the datasheet for many Xilinx FPGAs explicitly allow conduction in the ESD diodes as long as the current stays below a few mA. You are also right that many microcontroller datasheets don't say what the effect will be if you use the internal clamp didoes. Commented Jan 12, 2017 at 1:09