# maximum via current carrying capacity pcb

As I know, there exist limits on maximum current, a pcb via can tolerate before it melts before the via's temperature rises unacceptably high above ambient (say 10-100 C above ambient depending on application).

What are standard values or rules of thumb for the maximum current (or current density) through a pcb via?

PS: the question is about DC, but any additional considerations (if any) for a high frequency current are welcome as well.

Depends on hole dia and hole's inner plating thickness.

For example, a standard via with a plating thickness of 20um and with a diameter of 0.6mm allows 2.5ADC.

You can calculate by yourself: http://circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator/

• +1, why does allowable current depend on a via length? For a trace, the current capacity does not depend on its length but is governed by cross section (width and height), as I know. Commented Jan 12, 2017 at 10:13
• @SergeiGorbikov for a trace current capacity is highly dependent on length if you have limits to how much voltage drop over the trace you can handle. A trace rated for say 1A may have a voltage drop of 0.1V over 1cm, but if you have a 5V supply and a 25cm trace you will have zero supply voltage at the far end. Commented Jan 12, 2017 at 10:47
• @TomCarpenter 10x for your comment. Though, the question was not about IR drop. It was about current carrying capacity of a via. Commented Jan 12, 2017 at 11:32
• @SergeiGorbikov Actually, it's all about maximum allowed temperature rise. Think of it as a resistor: According to $\rho \cdot l / A$, resistance is directly proportional to its length. Thus, if we keep the current flowing through it constant, according to $I^2 R$, power consumption (so the temperature rise) will be higher for a longer via. In other words, if we allow less temperature rise then the via will allow less current. Note that not only via length, but all other parameters as well have a significant effect on this. Commented Jan 12, 2017 at 14:28
• @RohatKılıç I agree with your logic. Though, several things bother me. 1) Via temperature is an equilibrium value governed by heat exposed and heat consumed by the PCB. A longer via (or trace) has greater surface and thus greater heat outflow. 2) For traces, I've never seen limitations on length. It is about cross section, link. Also pls note the via calculator in the comment to the question - there is no length there 3) as a PCB designer, I don't have a lot of control over via length due to PCB stackup constraints. Commented Jan 12, 2017 at 14:57

The via melting means it got very hot. The melting point of copper is 1085 °C, so that's not the limiting factor. Bad things happen well below that:

1. The epoxy holding the copper to the board, and holding the board together turns to mush.

2. Even if the via and the board could take 1000 °C, silicon stops being a semiconductors at around 150 °C. There will be a significant area around the 1000 °C via that is at 150 °C or above. And, some of the ICs and other parts may only be rated for 80 °C or thereabouts.

3. It's going to take significant power to keep even a small point of a PC board at over 1000 °C. That power loss may not be acceptable to the circuit.

4. The voltage drop across the via will be significant for it to dissipate the power required to reach copper melting temperature. That voltage drop may cause problem to the circuit that is expecting the via to act like a wire.

To know what the characteristics of your vias are, talk to your board house. They should be able to tell you resistance and thermal resistance to ambient. From those you can compute other characteristics.

Advanced Circuits used to have a good on-line trace with calculator, which included vias if I remember right.

• +1, the notion about "melting" was incorrect (frankly, totally insane). I'll update the question, if you don't mind. Commented Jan 12, 2017 at 12:06

Since others have covered the DC current portion of your question, I'll add a little bit about designing vias for high frequency currents:

1. Surround the transition via with a ground plane, preferably surrounded by GND vias. This forms a "co-axial" transition structure for your signal.
2. Simulate the transition in a EM simulator if possible, like Keysight ADS or Ansys HFSS.
3. Avoid stubs in the via, either by backdrilling ($), using blind vias ($\$ + multiple lamination cycles), or just not having the via terminate on an outer layer. Backdrilling is usually the most common method for vias that terminate on an internal layer, so you want to keep your stub length below a quarter wavelength of your operating frequency if possible, because if your stub is a quarter wavelength, the signal reflecting off of it is 180 degrees out of phase with your main signal.

You can "cool" a via by using the traces at both ends to remove heat and dump that heat into planes, or simply move the heat away along the traces.

Should the trace on top of Via head off both left and right, you'll get twice as much cooling benefit at the top. Ditto for the bottom

Best case: the trace connects between Planes, with no thermal relief (no soldering expected), then you have EIGHT*2 paths for heat to travel out of that via, and life is nice and cool. Draw a 3 by 3 grid, with via in middle, and notice the 8 paths (each path is same size as via, so 70 degree Cent/watt) heat will use in exiting the via. The 8 paths produce 70/8 = 9 degree Cent/watt. And you have BOTH planes to remove heat. Now draw 5 by 5, 7 by 7, 9 by 9.

What is thermal resistance from midpoint of the Via (halfway thru the FR-4 epoxy fiberglass? 70degree/2 in each direction, or 35 degrees in each direction. Or 35 in parallel with 35, or 17 degree Cent/watt, if can dump heat into planes on both ends.

Standard 1-ounce-per-foot^2 foil (35 microns, 1.4 mils) has 70 degree C per watt per square of foil, for any size of foil. Get a quadrille pad, and draw some squares

• +1. With regards to 70 degrees C per Watt. Could you please elaborate more on it: 1) what is the source for the number, 2) ambient temperature assumed, 3) ambient medium assumed (fr4 or air)? 10x. Commented Feb 4, 2017 at 20:01
• Thermal resistance of copper is 1/340 watts/degreeC /meter Commented Feb 5, 2017 at 3:00
• (Was unable to type in full details in the allowed 5 minutes.) Scale up the thermal conductive from 1/340, by the ratio of 1 meter to 35 microns, and you get approximately 0.01 watt per degreeC. I assumed NO MOVEMENT OF HEAT out of the foil, only along the thin axis. Commented Feb 5, 2017 at 3:10
• The aspect ratio (circumference to board-thickness) of a via is approximately 1:1, thus there is 1 square of foil (granted the thickness may not be the 35 microns of the precision foil used in the PCB buildup) and the thermal resistance from the MIDDLE of the via is 1/2 of 1/2 of 70, or 18 degreeC/watt. Commented Feb 5, 2017 at 4:44