I'm trying to create a simple proof of concept regarding the configuration of our testbench (binding the correct entities to components/modules).
The structure is as follows:
I want to be able to control which VHDL entity sub_vhdl binds to, and which module sub_sub_verilog_2 binds to (for simulation in Questasim).
As far as I understand with a VHDL configuration file I can control the binding of sub_vhdl and sub_verilog, but it can not define the modules lower than sub_verilog.
And if I would write a verilog wrapper for the top entity I would have the opposite problem (not being able to control the binding of components to entities of the VHDL structure).
Is there a solution for my problem ? Some scripting (for example generating the VHDL config file with a script based on the situation) is not a problem.