Am I over-complicating this data acquisition design?

Question

I'm working on a project that involves periodically reading 16x 0~5V analog voltages from identical FSR voltage divider circuits using an ADC. Each FSR is connected to a gain/LPF stage before being read by an ADC. Each FSR's signal conditioning circuit is identical.

Originally, I was going to use 4x LM324's for the gain and filter stages of all 16 signals (along with all of the passives needed for the feedback networks). Having 16 of everything (including passives) seemed unnecessarily redundant if all of the gain/filter circuits were the exact same, so I thought about using an analog mux to switch between each FSR's signal, and have the muxed signal fed into a single signal conditioning circuit and ADC.

My reasoning behind this: if I needed to modify the gain/filter circuit, I could simply update the components once, as opposed to updating 16x of everything.

Currently, I'm implementing this design using a PSoC 5 LP, since it has the analog mux / op amp / ADC all in one package:

I am not well-versed in designing for multi-channel data acquisition applications like this, and would like to hear if this seems like a good/bad design, or if you think there is a better (or more elegant) way of approaching this task.

EDIT (1): The datasheet for the specific PSoC 5 LP chip (CY8C5888LTI-LP097) is located here. By "FSR", I mean "force sensing resistor". The set of 16 ADC measurements are taken at approximately 200 Hz (i.e. all 16 measurements must be taken in less than 1/200th of a second). I am currently operating the Delta-Sigma ADC at a 12-bit resolution. The output of each FSR voltage divider ranges from 0V (approx. 0 force applied to the FSR) to ~5V (maximum force before FSR saturates).

EDIT (2): The signals from the FSR voltage divider circuits would be in the low end of acoustic frequencies (the FSR's are measuring an occupant's exerted forces/pressure on the surface of an office chair), from roughly 500 Hz to DC (0 Hz) frequencies. I don't intend to capture all of the frequency content of the signals - hence the lower sampling rate.

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Also, here is an image of the voltage divider circuit for the force sensing resistors.

Answer 1

You can't time-domain multiplex a filter like that. The "state" of the filter (the voltage and/or current in the reactive components) is unique to each channel and would have to be multiplexed as well. This is very difficult to do without creating crosstalk among the channels; it's usually simpler to have a separate continuous-time filter for each channel.

Answer 2

Having worked at a telemetry house, right out of college, I provide this design. System must accurately read out 16 sensors, to 10 bit accuracy, 200 times a second. Assuming a single ADC, the start-conversion clock is 200*16 = 3,200Hz. To reject some of the Noise, we'll install passive RC filters in each of the 16 inputs to the 16-channel Analog Multiplexer (these passive filters are optional, but can be as SLOW as you need. The caps will also load the FSR output resistance, hence that resistance cannot be overlooked).

Assume 1/3200Hz or 300uS (microSeconds) to filter and sample and quantize. Any filter after the multiplexer will need time (time constants) to change from the prior FSR voltage to the new FSR voltage. For 10-bits, with 1.5 bit per tau, you must allow 7 tau for accurate rejection of prior voltage and settling to the new voltage. Assume 50% of the 300uS is used for filter settling; the filter Tau is 150uS/7 or 20uS, which is 50Krad/sec or 9,000 Hz F3dB. The ADC needs some time to acquire/sampled the multiplexed voltage; we'll assume 5 uS sample-time and 145uS conversion time, thus a 14uS clock to a successive approximation ADC.

Here is the Sampling Worksheet[for 12 bits, with ADC grabbing a sample in the very last point of that settling] from Signal Chain Explorer

Here is the ADC timing worksheet[ note the R+C input TAU of the ADC sets the upper frequency for accurate ADC track/hold behavior ] []2

Here the Johnson/Boltzmann/KT noise analysis shows the opamp, providing 80dB gain, allows only 9 bits resolution. And we've not evaluated the interferers.

Answer 3

Your design looks reasonable. Depending on the desired low pass response and the date rate you need, you may need to add a filtering state in software to address the settling time other mentioned. That is, sample at a higher rate than your application needs, reduce the time constant of the analog filter to be fast enough for the sampling rate and then do additional low pass filtering in software (one per channel). Simple low pass filters are easy to implement in software. E.g. something like values[channel] += (new_sample[channel] - value[channel]) / k, where k is a value > 1. If k is let's say 16 then you just shift right by four.