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I'm working on a project that involves periodically reading 16x 0~5V analog voltages from identical FSR voltage divider circuits using an ADC. Each FSR is connected to a gain/LPF stage before being read by an ADC. Each FSR's signal conditioning circuit is identical.

Originally, I was going to use 4x LM324's for the gain and filter stages of all 16 signals (along with all of the passives needed for the feedback networks). Having 16 of everything (including passives) seemed unnecessarily redundant if all of the gain/filter circuits were the exact same, so I thought about using an analog mux to switch between each FSR's signal, and have the muxed signal fed into a single signal conditioning circuit and ADC.

My reasoning behind this: if I needed to modify the gain/filter circuit, I could simply update the components once, as opposed to updating 16x of everything.

Currently, I'm implementing this design using a PSoC 5 LP, since it has the analog mux / op amp / ADC all in one package:

PSoC Creator Schematic

I am not well-versed in designing for multi-channel data acquisition applications like this, and would like to hear if this seems like a good/bad design, or if you think there is a better (or more elegant) way of approaching this task.

EDIT (1): The datasheet for the specific PSoC 5 LP chip (CY8C5888LTI-LP097) is located here. By "FSR", I mean "force sensing resistor". The set of 16 ADC measurements are taken at approximately 200 Hz (i.e. all 16 measurements must be taken in less than 1/200th of a second). I am currently operating the Delta-Sigma ADC at a 12-bit resolution. The output of each FSR voltage divider ranges from 0V (approx. 0 force applied to the FSR) to ~5V (maximum force before FSR saturates).

EDIT (2): The signals from the FSR voltage divider circuits would be in the low end of acoustic frequencies (the FSR's are measuring an occupant's exerted forces/pressure on the surface of an office chair), from roughly 500 Hz to DC (0 Hz) frequencies. I don't intend to capture all of the frequency content of the signals - hence the lower sampling rate.


Also, here is an image of the voltage divider circuit for the force sensing resistors.

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    \$\begingroup\$ Data sheet for PSoC 5 LP required. Please provide link. Also, what refresh rate are you considering? How much settling time have you estimated (big signal to a small or negative signal)? What bit-depth for the ADC? What are your input signals precisely? What is "FSR"? Leave all your answers in the question - don't start documenting stuff as comments. \$\endgroup\$ – Andy aka Jan 12 '17 at 15:01
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    \$\begingroup\$ Have you accounted for the fact that your single filter will need time to settle every time the mux switches to a new channel? \$\endgroup\$ – brhans Jan 12 '17 at 15:09
  • \$\begingroup\$ I briefly considered that before, but I definitely need to re-think the design now that you and @DaveTweed mention that! \$\endgroup\$ – JFET Buffer Jan 12 '17 at 16:31
  • \$\begingroup\$ Is your algorithm just to select a new mux channel, wait for it to settle then sample the near-DC level? (might oversample it and filter those to reject noise but effectively a single sample) Or do you intend to do something different? Thanks. \$\endgroup\$ – TonyM Jan 12 '17 at 19:40
  • \$\begingroup\$ At the moment, I just have all the channels being sampled as fast as possible at every 1/200th of a second. So once every 1/200 s the PSoC will measure/mux/measure/mux/... until all 16 readings / ADC conversions have been stored in a buffer. After the 16 readings from the FSR's, the accelerometer data from an IMU is stored. After the FSR and IMU measurements are done, I transmit the entire set of data via UART to a separate MCU that handles mass storage devices and Wi-Fi comms. Note: The UART transmissions don't take place every 1/200th of a second; they take place around once every 5 seconds. \$\endgroup\$ – JFET Buffer Jan 12 '17 at 19:51
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You can't time-domain multiplex a filter like that. The "state" of the filter (the voltage and/or current in the reactive components) is unique to each channel and would have to be multiplexed as well. This is very difficult to do without creating crosstalk among the channels; it's usually simpler to have a separate continuous-time filter for each channel.

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  • \$\begingroup\$ Mux-ing a sigma-delta A-to-D requires a settling period too, although as you say, time for low-pass filter to settle would dominate. \$\endgroup\$ – glen_geek Jan 12 '17 at 16:28
  • \$\begingroup\$ Those are both excellent points, there. Would you say it would be best to just stick with the original idea of having the individual signal conditioning circuits fed into some multi-channel ADC? I was originally aiming to lower the component count when I design the PCB for this (hence the use of the PSoC), but I would definitely want choose the solution works the best for the overall design. \$\endgroup\$ – JFET Buffer Jan 12 '17 at 16:44
  • \$\begingroup\$ @glen_geek: Yes, a delta-sigma converter implicitly includes a filter, and the same rules apply. \$\endgroup\$ – Dave Tweed Jan 12 '17 at 17:26
  • \$\begingroup\$ Yes, do that, @JFETBuffer. Multi-Opamp-ICs and capacitor and resistor networks help making such designs halfway tolerable to build. \$\endgroup\$ – Marcus Müller Jan 12 '17 at 17:27
  • \$\begingroup\$ I also think it's a good idea for me to go with that design. Now that I think of it, the PSoC might not be needed after all. Although I could use 16ch on the built in ADC's, I'm thinking it might be better to just switch to a setup with 2x 8ch external ADC's (ex: MCP3208) to an AVR or MSP430 to lower the cost a bit. Do you agree/disagree with this idea? \$\endgroup\$ – JFET Buffer Jan 12 '17 at 17:50
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Having worked at a telemetry house, right out of college, I provide this design. System must accurately read out 16 sensors, to 10 bit accuracy, 200 times a second. Assuming a single ADC, the start-conversion clock is 200*16 = 3,200Hz. To reject some of the Noise, we'll install passive RC filters in each of the 16 inputs to the 16-channel Analog Multiplexer (these passive filters are optional, but can be as SLOW as you need. The caps will also load the FSR output resistance, hence that resistance cannot be overlooked).

Assume 1/3200Hz or 300uS (microSeconds) to filter and sample and quantize. Any filter after the multiplexer will need time (time constants) to change from the prior FSR voltage to the new FSR voltage. For 10-bits, with 1.5 bit per tau, you must allow 7 tau for accurate rejection of prior voltage and settling to the new voltage. Assume 50% of the 300uS is used for filter settling; the filter Tau is 150uS/7 or 20uS, which is 50Krad/sec or 9,000 Hz F3dB. The ADC needs some time to acquire/sampled the multiplexed voltage; we'll assume 5 uS sample-time and 145uS conversion time, thus a 14uS clock to a successive approximation ADC.

Here is the Sampling Worksheet[for 12 bits, with ADC grabbing a sample in the very last point of that settling] from Signal Chain Explorer enter image description here

Here is the ADC timing worksheet[ note the R+C input TAU of the ADC sets the upper frequency for accurate ADC track/hold behavior ] [enter image description here]2

Here the Johnson/Boltzmann/KT noise analysis shows the opamp, providing 80dB gain, allows only 9 bits resolution. And we've not evaluated the interferers. enter image description here

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Your design looks reasonable. Depending on the desired low pass response and the date rate you need, you may need to add a filtering state in software to address the settling time other mentioned. That is, sample at a higher rate than your application needs, reduce the time constant of the analog filter to be fast enough for the sampling rate and then do additional low pass filtering in software (one per channel). Simple low pass filters are easy to implement in software. E.g. something like values[channel] += (new_sample[channel] - value[channel]) / k, where k is a value > 1. If k is let's say 16 then you just shift right by four.

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  • \$\begingroup\$ See my comment to TonyM \$\endgroup\$ – Dave Tweed Jan 12 '17 at 17:08
  • \$\begingroup\$ Your comment was about a filter between the mux and the adc. My reply here is about having a filter after the adc. That is, sample fast and implement the filter in software, one per channel. \$\endgroup\$ – user1139880 Feb 13 '17 at 5:11
  • \$\begingroup\$ A digital filter after the ADC can't do anything to prevent aliasing, which is presumably why the OP was considering analog filters in the first place. And if aliasing is not a concern, then there's no point to having an analog filter at all. So my comment regarding your thoughts on the analog filter are still completely appropriate. \$\endgroup\$ – Dave Tweed Feb 13 '17 at 12:47

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