As in, you choose what you want the nodes to function as then the software fills in an optimized logic design for you? seems like it would be simple enough. perhaps only fill in 70% or so and you do the rest?

  • \$\begingroup\$ David Johannson of Silicon Compilers built the first such. I believe Synopsis acquired that company. \$\endgroup\$ – analogsystemsrf May 26 '17 at 6:46

They're called FPGA Design tools. See Xilinx.com, lattice.com, altera.com. Simple in concept. Prepare to devote your life for the next 6 months to learn how to use them.


As @FiddyOhm has said, you can do what you're suggesting in VHDL or Verilog and you can get free and comprehensive development software to try from their website. I'd personally recommend Altera's Quartus as the friendliest of them to try as a newcomer but they're all pretty straightforward once you've learnt a few basics.

You can essentially Lego together existing logic blocks, although that naturally only gives you the functions that are already designed and available. I can't speak for Verilog but VHDL already has levels of abstraction away from logic gates so just designing in VHDL gives you some of what you describe.

You obviously need to specify your design exactly so you would need to understand VHDL/Verilog well.

You haven't described your experience so far or detailed your expectations for the design software you'd imagined, so it's hard to advise you further.

  • \$\begingroup\$ Verilog has much the same level of abstraction as VHDL. In some ways more e.g. we all know that an integer is going to be represented as a 2s compliment value yet VHDL requires an explicit conversion before allowing you access to individual bits, verilog doesn't. As with most things that makes life easier this is both good and bad. \$\endgroup\$ – Andrew Jan 13 '17 at 11:04
  • \$\begingroup\$ Thanks, @Andrew. I guessed you could do it, as both VHDL and Verilog have survived as rivals for so long, but don't want to speak definitely about something I've no experience in (a rarity on this site :-) ) \$\endgroup\$ – TonyM Jan 13 '17 at 11:06

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