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I'm looking at the schematic of the AM3354 EVM and I don't know why I see so many of the same value capacitors used in parallel and typically around the processor or memory.

I understand that different capacitors will have different self resonant frequencies and perhaps that is advantageous for noise filtering but why so many of the same value? Isn't one sufficient?

This question is based around the same value of components not simply combining different value capacitors into one larger capacitance part.

TI AM3354 EVM Base board schematic

Capacitor array

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    \$\begingroup\$ Because ESR and ESI are a thing \$\endgroup\$
    – PlasmaHH
    Jan 13, 2017 at 16:19
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    \$\begingroup\$ Also, please see this question. \$\endgroup\$
    – bitsmack
    Jan 13, 2017 at 17:12

5 Answers 5

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If you count the power pins on the IC, and the supply decoupling caps of the same value, you'll probably find a 1:1 correspondence. This indicates you are expected to place one per power pin, as close as practical to the pin, to minimise the effects of trace inductance.

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    \$\begingroup\$ +1. That processor has 9 pins/balls connected to VDDSHV6, but they are so close together that it makes it impractical to place a 10nF cap per pin. 6 is the best you can do. \$\endgroup\$
    – Steve G
    Jan 13, 2017 at 16:31
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They are usually just multiple decoupling capacitors on the various pins of a IC that are cumbersome to show in their physical location to each pin on a schematic.

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  • \$\begingroup\$ Thanks. Yeah that makes sense that they would be in a group on the schematic but at the pins on the PCB layout. \$\endgroup\$
    – Samee87
    Jan 13, 2017 at 16:59
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This is not typical, but... I once had to change a design to use multiple smaller value caps because the mechanical team made the fit so tight that the larger valued caps we could get were simply too tall. We could get shorter caps, but not in time for our deadline, so we punted and used smaller valued, shorter caps and got the prototype ready for its demo.

As far as I know, the smaller caps were retained into production.

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  • \$\begingroup\$ Yeah I know the pain of dealing with Mechanical. Sheesh. \$\endgroup\$
    – Samee87
    Jan 13, 2017 at 16:58
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    \$\begingroup\$ Actually, I must say that working in an environment with active Electrical, Software, and Mechanical engineering groups was one of the most interesting and satisfying assignments I've ever had. \$\endgroup\$
    – Peter Camilleri
    Jan 14, 2017 at 17:32
  • \$\begingroup\$ You're fortunate then. In my limited experience and among other design physical concerns, Mechanical & Industrial Design dictate much of where we can place certain connectors which as you know can potentially have a negative impact on emissions. Usually software and hardware are more understanding of each other's needs. \$\endgroup\$
    – Samee87
    Jan 16, 2017 at 19:13
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Because large caps also mean large internal resistance and large inductance. By putting small caps in parallel, you can still get the same capacitance, at the same time, smaller total ESR compared to a single big cap. Possible duplicate here: Why too many capacitors in parallel for Vdd supply net? Can't we just add all to replace with one big capacitor?

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Other answers have covered the one-decoupling-cap-per-power-supply-pin point.

You'll also notice that one of the caps is a 10uF. Typically this would be an electrolytic cap. Electrolytics are good at storing a large amount of charge (they have high capacitance for their physical size) but typically also have a high parasitic impedance which slows down their provision of that stored charge to the device. When dealing with devices drawing significant current and/or at the end of long power supply tracks, it's common to use a small high-speed capacitor in parallel with an electrolytic. The latter handles larger changes in voltage slowly, and the former handles smaller changes in voltage quickly. It's a fairly intuitive principle, and one which in practise works very well.

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  • \$\begingroup\$ That makes sense. I'll try to employ a similar practice next time a lay out a small board space permitting of course. \$\endgroup\$
    – Samee87
    Jan 13, 2017 at 20:24

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