I was looking at a board schematic and noticed something odd. All the IO pins are identical in function. But for some reason, there is one IO pin that has both a pull up resistor and a capacitor to ground connected to it (while all the others have nothing). Why is this?

(The IO pins come from a CycloneII EP2C5 FPGA if that's relevant info. I've looked at the pin out documentation for the chip but there's nothing particularly special about this pin. The FPGA is mounted on a bare bones general purpose development board, and as such has no specific intended function. And all the circuitry on the board is just supporting circuitry like power.)


  • \$\begingroup\$ Was it connected to a button? \$\endgroup\$ – Bradman175 Jan 14 '17 at 7:50
  • \$\begingroup\$ No, it's just hanging out on its own \$\endgroup\$ – Jet Blue Jan 14 '17 at 8:19

As this is related to an FPGA, any pin can have pretty much any imaginable function. It depends on the software in the FPGA what the pin will be used for.

In this case the pin is most like used as INPUT, possibly as RESET-pin or similar. If the pin was used as an OUTPUT, the output driver would have a hard time charging the capacitor and is easily overloaded, hence OUTPUT config is quite unlikely.

What happens during power on of the circuit, is the pin is pulled low by the uncharged capacitor long enough for the logic circuit programmed in the FPGA to be used as a RESET signal while the power supply stabilizes. I expect the pin logic level to toggle LOW to HIGH after about (order magnitude) 10kΩ × 10µF =~ 100ms after power on.

The only thing that does not make sense to me here is how the cap will discharge when the circuit is powered off. Probably the internal protection diodes of the FPGA are used for that purpose.

  • \$\begingroup\$ Thanks for the answer! So whoever designed the board wanted to give users the option to use the pin as a RESET pin? \$\endgroup\$ – Jet Blue Jan 14 '17 at 8:32
  • \$\begingroup\$ Possible. Hard to tell without knowing where the circuit originated from. @JetBlue \$\endgroup\$ – jippie Jan 14 '17 at 8:33
  • \$\begingroup\$ The cap will discharge because VCC3.3 will be 0 volt when the board is powered off. \$\endgroup\$ – Martin Zabel Jan 14 '17 at 15:30
  • \$\begingroup\$ Updated the question, the circuit is from a bare bones development board. The only circuitry on it is what's needed to power and program the FPGA. So the FPGA has no specific intended use. \$\endgroup\$ – Jet Blue Jan 14 '17 at 16:39
  • \$\begingroup\$ @MartinZabel you probably want a reset upon any power failure, however short it is. Discharge through the resistor is slow and the FPGA state can get corrupted due to low power supply. Usually with a reset circuit you'll have a reverse diode in parallel to the resistor to ensure the cap discharges immediately with the power supply. Anyway, the design probaby relies on the on-chip ESD protection diodes. \$\endgroup\$ – jippie Jan 15 '17 at 7:38

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