# how many bits a random-access memory's cell contains?

this question has something to do with programming but since it masters the hardware layer I created a new account here to avoid being out-of-scope on stack overflow.

I'm quite novice in the hardware field, I'd like to know how many bits a RAM's cell contains.

For example :

I define a var (int)

Knowing that an integer is 32 bits, if the location of var is let say 0x125 :

• is the system reminding var as the value contained from 0x125 to 0x158 (32 bits allocated)

or

• is it just reminding the location 0x125 of the cell that contains a particular number of capacitors (regarding the technology of the memory card) ?

in other words : is the address pointing to a set of bits or is the address pointing just one bit (the number of bits to read from that position would be determined by the system) ?

Any reviews would be much appreciated.

There is almost no chance that your memory is bit-addressed. The most likely situation is that your addresses are byte-addresses. And when you get the value of a 32-bit variable, the question is whether that address points at the Most Significant Byte or the Least Significant Byte of that 4-byte value - which is architecture dependent (e.g. x86 is little-endian, while MIPS is big-endian).

To give you an example in C, assuming your variable var has the value 0xDEADBEEF it might be stored in memory in one of two ways:

Big-Endian (because the address 0x125 points to the MSB)

-------------+--------+--------+--------+--------+
base address |              offset               |
-------------+--------+--------+--------+--------+
|    0   |    1   |    2   |    3   |
-------------+--------+--------+--------+--------+
0x125    |  0xDE  |  0xAD  |  0xBE  |  0xEF  |
-------------+--------+--------+--------+--------+


or Little-Endian (because the address 0x125 points to the LSB)

-------------+--------+--------+--------+--------+
base address |              offset               |
-------------+--------+--------+--------+--------+
|    0   |    1   |    2   |    3   |
-------------+--------+--------+--------+--------+
0x125    |  0xEF  |  0xBE  |  0xAD  |  0xDE  |
-------------+--------+--------+--------+--------+


As the granularity of access to the memory at the instruction set level is likely no smaller than a byte, if you want to modify individual bits, you need to read from the memory at its minimum granularity (likely a byte), modify its contents with bit-manipulation operations (|, &, ~, etc.), and write back the memory.

In integrated circuit design, a "memory cell" is an arrangement of transistors and wires used to store a single bit. A pattern covering some area on the chip, and more-or-less the identical pattern is repeated many times, tiled and packed together with no gaps between them. (When each cell contains one transistor and one capacitor, it's a DRAM chip. When each cell contains one transistor and a floating gate, it's a Flash chip. When each cell contains 10 transistors, it's a 10T SRAM chip. When each cell contains 6 transistors, it's a 6T SRAM chip. Etc.)

The vast majority of memory cells can store exactly 1 bit per cell. (The only exception I know of is a few flash chips that have multi-level cell).

The vast majority solid-state memory stores 8 bits of data at each address. And therefore "reading an address" almost always involves reading-out the state of 8 distinct memory cells. Some hardware is arranged such that those 8 cells are near each other; other hardware is arranged such that those 8 cells attached to that address are on completely separate chips. (Some of the rare exceptions include the 14-bit-wide program memory in some PIC processors, the 36-bit-wide memory of most of the early pre-microprocessor computers, etc.)

As you have already guessed, the address is pointing to a set (of 8) bits.

As vicatcu explained, things that require more than 8 bits -- such as 32-bit integers -- are stored in several consecutive bytes at several consecutive addresses.