I am trying to capture pixel data going to a small B&W CRT display. The signals I have to work with are the TTL-level pixel data signal, HSYNC, and VSYNC. I know the pixel clock frequency (~16 MHz) but for my application, I have no access to the pixel clock signal.
I want to sample the pixel signal at the appropriate time (during the middle of the bit period, not during the transition), so I figured I need to generate a new 16 MHz clock with some phase relationship to an edge of the HSYNC signal and use that to sample the pixel signal.
I know how to use a PLL to multiply a clock signal and maintain a certain phase relationship between the input and output, but how do I maintain a similar relationship between a new 16 MHz clock and a signal that only occasionally has an edge (HSYNC)?
Or is there a better way to solve this problem?