I have been refreshing my memory on pipelined processors for fun. Currently, I'm reviewing interrupt implementations in (in-order) pipelined CPUs, and various complications that arise. I've found this PDF to be helpful, but it leaves some questions as exercises to the reader.
One of these questions is:
What makes precise interrupts hard? Delayed branches cause a problem. What is it?
My educated guess is that "if an exception or I/O interrupt happens in a delay slot, state about the processor having a branch pending- exclusive to delay slots- is not accounted for when restarting the instruction.
My solution would be to create some state that indicates we are within a delay slot, along with information about the result of the branch. This should work because if the delay slot faults, the branch will complete so that sequential execution of instructions matches pipelined execution.
However, I'm not confident in my solution is correct. Is there some other state or explanation I may be missing?