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I understand that the capacitance of a ceramic cap is very dependent on the DC bias applied to the terminals. At rated voltage, I've measured a decrease of up to 70%, and I've heard it can go higher. That's two datapoints, one at zero voltage, and one approximate value at rated voltage. For cases where the manufacturer doesn't make the derating curves available, I'd like to be able to estimate the derating required.

From a TDK app-note (app-video? Do we have a name for these things, yet?), I grabbed this plot. Smaller capacitance components suffer less capacitance change, higher voltage components suffer less capacitance change at the operating voltage, and (not shown) larger components suffer less capacitance change.

cap derating curve Source https://www.youtube.com/watch?v=weUrWSFJCgk TDK Tech Tube : DC Bias Effect on Multilayer Ceramic Capacitors (MLCC)

Is there a standard curve for this? Something like how there's a standard capacitor discharge curve, for example. I'd like to be able to fit to the datapoints and interpolate for an operating voltage somewhere below the rated voltage. Are there other techniques, short of ordering the component and measuring, to estimate the capacitance at operating voltage?

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    \$\begingroup\$ Last time I checked - no. Each manufacturer, size and dielectricum has its own curve. \$\endgroup\$ – winny Jan 16 '17 at 22:22
  • \$\begingroup\$ I noticed in LTpowerCAD that the caps have C nominal, C at half rated voltage, and C at rated voltage fields. I wonder if anyone's got some insight into how they work that? Fit a parabola? SPICE sim behind the scenes? \$\endgroup\$ – Jason_L_Bens Jan 16 '17 at 22:34
  • \$\begingroup\$ As @winny says, there seems to be considerable variation between manufacturers. Often you have to go beyond the datasheet to use software or web-based information from the maker. If they don't supply it, then you're in the dark. \$\endgroup\$ – Spehro Pefhany Jan 16 '17 at 23:10
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    \$\begingroup\$ My go-to application note on the subject: Temperature and Voltage Variation of Ceramic Capacitors, or Why Your 4.7µF Capacitor Becomes a 0.33µF Capacitor. \$\endgroup\$ – Nick Alexeev Jan 16 '17 at 23:35
  • \$\begingroup\$ Peripheral: As you care about ceramic characteristics more than many (as one should :-) ). Be aware that ceramic caps can exhibit ringing when hit with a step waveform and at eg power turn on have been known to cause voltage spikes high enough to destroy eg following regulators. | Microphonic effects may happen - percussion to signal. \$\endgroup\$ – Russell McMahon Jan 17 '17 at 0:02
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Always refer to the datasheets. Since there are literally hundreds of ceramic series of caps the genreral properties are similar for each material types but degrade with increased capacitance, and improve if you over-rate the voltage.

The quality grades are inversely related to a cost and impact, although minor unless you are dealing in high volume of parts. COG are low k dielectric so very limited in max. value compared to the other families.

The best for voltage and piezo insensitivity are COG a material type equivalent to the tempco category NP0, aka Neg/pos/zero temp. coefficient (<50ppm/'C) There are other material letters types which correspond to N100, N200 etc to N1000 shown in the 1st top left graph. P150 are rare but exist for coil compensation.

The next graph top right shows the high k dielectric constant, Y5V intended for room temp apps which are lowest cost compared with X5R.

The next row shows the impedance series resonant frequency, SRF for a given small Murata 0402 SMD package in COG vs X7R/Y5U materials.

enter image description here The DC Voltage capacitance drop is shown next which for X7R/X5R never drops more than 30% for these parts and for your TDK chart <=20% This is a good general purpose type where if your circuit sensitivity is very low to value. Otherwise, you would choose NP0.

Next the AC impedance drops with rising AC voltage shown as a rising capacitance for non COG types. Note the measurement standard frequencies are higher for COG. enter image description here

Next shows the typical aging reductions in C value often defined by operating at 70% or 80% V ratings for these ceramic material categories.

The last shows the impact of ESR on ceramic caps and their ability to dissipate heat by nomographs of VA, V and I vs F & C values for these 0402 SMD parts.

If you derate voltage by 33% ,minimum you can expect >80%C due to supply sensitivity from all vendors with TDK better than many others. For high Q caps in RF, and low Q Caps for SMPS filters, Murata has many excellent choices as well in wide low ESL geometries.

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    \$\begingroup\$ +1 for mentioning aging, which isn't talked about as much as temperature or DC bias derating. Murata's always got such great datasheets, but what do you do when the component you like doesn't have this information available? I can bury the FAEs under a pile of emails until they cough up the plots, but I was hoping there was some way to estimate the reduction without the delay while the FAE checks in with his component engineer and reports back. \$\endgroup\$ – Jason_L_Bens Jan 16 '17 at 23:15
  • \$\begingroup\$ you will get a +1 if you work out the ESR * C time constant from the graphs \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 17 '17 at 0:19

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