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If I'm correct that FPGA lookup tables usually have one output, is it the routing structures that would be used to duplicate them? Wouldn't that mess with input voltage requirements for other LUTs?

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  • \$\begingroup\$ Why a single gate output is not triggering similar question? \$\endgroup\$ – Eugene Sh. Jan 17 '17 at 21:52
  • \$\begingroup\$ @EugeneSh. I don't understand. \$\endgroup\$ – 0joshuaolson1 Jan 18 '17 at 19:30
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In the classical architecture, you have unlimited fan out on your s-blocks, so you can copy the output to another routing line, but due to the nature of topology and graphs you most likely would duplicate the logic on a LUT. To give you a feel, here's a copy of an old fuse chart that I used when I was teaching FPGA design class.

CLB

You can imagine that the output is not fanout limited. Below is an example of a single output driving two routing lines. This means you can duplicate the output by either mirroring the LUT or fanout on the output.

dogleg

In the image above, you see how the logic conceptually moves around.

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  • \$\begingroup\$ Am I seeing two inputs combined into one without a logic block involved? In addition to voltage requirements (which I imagine are also affected by distance), what's going on here? \$\endgroup\$ – 0joshuaolson1 Jan 18 '17 at 19:39
  • \$\begingroup\$ You are seeing an output line being tied into TWO different routing lines that are then going to TWO different CLB inputs. This is a "dog-leg" logic copy. Whether you use a dog-leg, or copy the input by using two CLBs will depend on what the graph looks like. Look at this document (pwp.gatech.edu/wp-content/uploads/sites/367/2016/03/…), this is the overview from when I taught FPGA design. \$\endgroup\$ – b degnan Jan 18 '17 at 20:13
  • \$\begingroup\$ Ha, I was reading the routing from input line to output line. \$\endgroup\$ – 0joshuaolson1 Jan 18 '17 at 22:05

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