Is there any equation which can answer the max allowable distance for the decoupling capacitor to be placed for a max. frequency that is used?
There isn't a fixed equation that relates maximum decoupling cap distance to maximum frequency because there isn't a fixed relationship in the first place.
The problem comes down to not being able to know all the relevant parameters to decide exactly what you can get away with. Therefore, we generally over-design and don't push things to the limit.
Decoupling caps are the first parts you should place after placing a chip. Look at which pins each decoupling cap must connect between, and place the decoupling caps to keep the leads as short as reasonably possible.
So how far can you go? Will a extra millimeter matter? A extra 5 mm? One inch? Dirty Harry had a good answer to this: Do you feel lucky? Well, do you, punk?
Rise and fall times of the transition currents are the source of emmision problems and voltage dips. Always try to limit the induced emmision by minimizing the current loop as much as possible by placing the decoupling as close as possible to all your power supply pins. Don't forget to use a solid ground plane as close to the chip as possible.
Do you want impressive results in the test lab: use three-terminal Capacitor, add decoupling symmetrically around the chip to cancel out the induced opposite fields, add an LC filter for your local chip power supply, use at least a 4 layer board with ground planes on inner layer 1 and bottom and add via stitching over the entire board. Power planes high speed and long traces on inner 2 sandwiched by ground planes.
If there is no space left for your decoupling. Create the space by using multilayer boards. Less emmision -> less trouble.