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Is there any equation which can answer the max allowable distance for the decoupling capacitor to be placed for a max. frequency that is used?

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    \$\begingroup\$ No there is not.To do a theoretical estimate of the maximum distance you would need some information which is not always easy to determine, for example: how much signal at what frequencies is allowed on the supply line (and ground as well), how much signal/current at that frequency is generated on those lines ? What will be the most critical signal frequency ? Under what condition will supply ripple cause a problem ? That is too much work to determine properly. So experienced PCB designers place the decoupling as close as possible and use experience to decide if that is close enough. \$\endgroup\$ – Bimpelrekkie Jan 18 '17 at 11:13
  • \$\begingroup\$ The answer is yes, or certainly that one can be derived. But you wouldn't want to work with it, it'll be far longer and complicated than it will be productive. As @FakeMoustache says, follow guidance from experienced layout engineers either in person or from online references. Is this question in response to a specific problem you have? \$\endgroup\$ – TonyM Jan 18 '17 at 11:22
  • \$\begingroup\$ I have a max driven signal frequency of 125MHz, now i want to know how much far the decoupling 100nF caps can be placed, so that signal will be in the acceptable range of integrity? \$\endgroup\$ – maheshprajapati Jan 18 '17 at 12:05
  • \$\begingroup\$ @Tony: I see your point that a mathematically describable relationship must exist. However, the problem is that some of the inputs to that equation will be parameters you don't know. For example, what is the largest step in current draw of the chip over 1 ns, 5 ns, 10 ns? At what combination of voltage dip and dV/dt does the chip stop operating correctly? \$\endgroup\$ – Olin Lathrop Jan 18 '17 at 12:13
  • \$\begingroup\$ The decoupling caps are there to decouple the supply of the ICs which work with your signal. The decoupling caps do not have a direct relation to signal integrity. \$\endgroup\$ – Bimpelrekkie Jan 18 '17 at 12:13
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There isn't a fixed equation that relates maximum decoupling cap distance to maximum frequency because there isn't a fixed relationship in the first place.

The problem comes down to not being able to know all the relevant parameters to decide exactly what you can get away with. Therefore, we generally over-design and don't push things to the limit.

Decoupling caps are the first parts you should place after placing a chip. Look at which pins each decoupling cap must connect between, and place the decoupling caps to keep the leads as short as reasonably possible.

So how far can you go? Will a extra millimeter matter? A extra 5 mm? One inch? Dirty Harry had a good answer to this: Do you feel lucky? Well, do you, punk?

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Rise and fall times of the transition currents are the source of emmision problems and voltage dips. Always try to limit the induced emmision by minimizing the current loop as much as possible by placing the decoupling as close as possible to all your power supply pins. Don't forget to use a solid ground plane as close to the chip as possible.

Do you want impressive results in the test lab: use three-terminal Capacitor, add decoupling symmetrically around the chip to cancel out the induced opposite fields, add an LC filter for your local chip power supply, use at least a 4 layer board with ground planes on inner layer 1 and bottom and add via stitching over the entire board. Power planes high speed and long traces on inner 2 sandwiched by ground planes.

If there is no space left for your decoupling. Create the space by using multilayer boards. Less emmision -> less trouble.

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