I am programming a Cortex M3 bare-metal to talk with SPI Flash. One of the configuration bits of an SPI control register is FRF (Frame format). It can either be set to SPI Motorola mode (0) or to SPI TI mode (1). (See the ARM reference manual page 695 here.)
The datasheet of the SPI Flash (available here) does not give indication regarding which mode I should use.
What are the two different modes, and which should I use for the specific Flash chip I am using?
Motorola and TI mode refer to different configurations of clock polarity (CPOL) and clock phase (CPHA). The clock polarity dictates whether a high or low signal marks a clock, the phase tells the device when to sample the data line.
According to your ARM datasheet, you can set CPOL and CPHA for your SPI controller.
Your flash chip (See chapter 3) supports {CPOL=0, CPHA=0} or {CPOL=1, CPHA=1}.
For more information, http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus#Clock_polarity_and_phase
{CPOL=0, CPHA=0} Motorola or TI?
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Commented
Mar 16, 2012 at 14:09
A brief glance at the ARM data sheet would suggest that the main difference between the TI mode and Motorola mode have to do with their handling of an output signal called SSPFSSOUT which many devices simply don't need. This signal is supposed to pulse high between bytes, so as to indicate which bit of each byte should be considered the first. In TI mode, it goes high during the transmission of the last bit of a byte, while in Motorola mode it goes high and then low between bytes. The flash chip wants a chip-select signal that is held low for the entire duration of a transaction, so an output that goes high between bytes won't be useful for it.
I would expect that even when SSPFSSOUT isn't used, Motorola mode would make data easier to read on a scope (since there would be a pause after every byte), but TI mode might be faster (since it wouldn't waste any time pausing between bytes). What's important, however, is to ensure that the sequence of signals the controller generates meets the requirements given in the peripherals' data sheet.
It seems (previously) Motorola processors had something called big endian mode for their registers in which if the SPI master communicates with a slave device which has little endian registers, you have to convert the data received from the slave to big endian and you have to convert data from big endian to little endian while sending data to the slave.
In big endian registers, the most significant bit (MSB) is at bit 31 in a register of length 32 bits. The least significant bit is at bit 0. In Little endian registers, MSB and LSB are reversed. While reading registers, you have to make sure you read the correct order of MSB and LSB and hence the conversion for endianness is necessary while transferring data between big endian and little endian systems.
