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schematic

simulate this circuit – Schematic created using CircuitLab

I'm expected to design a pnp common emitter amplifier. The gain should be 13 and the output 2Vp-p. Vcc is -13V. The load resistance is 1728 ohms. I've calculated the ac source voltage by using the gain formula Av=Vout/Vin to be 77mV. The other gain formula Av=Rc/RE I used to get an idea of the swamping emitter resistor to get a 13 gain. How do I get the rest of the resistor values if I'm using voltage divider bias? Is my work thus far correct? I've simulated the circuit with arbitrary values but need to know a the proper design process.

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    \$\begingroup\$ Provide a schematic to provide the overall topology of what you've done, already. Don't worry about exact values. Just the overall shape is what's important in clarifying where you are at right now. Use the schematic editor that is included here. \$\endgroup\$ – jonk Jan 22 '17 at 18:48
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    \$\begingroup\$ Doesn't anyone follow the basic rules of schematics any more? Like, positive at the top, negative at the bottom, etc? \$\endgroup\$ – Ian Bland Jan 22 '17 at 19:32
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    \$\begingroup\$ @IanBland Well, at least there's a schematic now. That's a little more than 100 times better than nothing. \$\endgroup\$ – jonk Jan 22 '17 at 19:43
  • \$\begingroup\$ If you are required to design a gain value as exact as possible you should not use the rough approximation Rc/RE. Instead, use the correct formula involving the transconductance gm. \$\endgroup\$ – LvW Jan 22 '17 at 20:25
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Assumption:- With an operating frequency of 10kHz your 10uF capacitors are effectively short circuits at AC compared to other impedances in the circuit.

First thing to do, and most difficult is to decide what your collector current is going to be. It has to be high enough to drive your output impedance in parallel with the dc setting resistor Rc, with Rl at about 1.7k with a voltage swing of 2Vpp you need a current swing of about 1.2 ma in the load. I am going to pick a DC current of 5ma in the collector this gives me the room to drive the load and is well within the transistors best operating region.

Next what is Rc? We usually try to set Collector voltage at half the supply to give maximum positive and negative excursion. This would give Rc=6.5V/5ma = 1.3k.

Now lets look at the emitter resistors. For good DC stability we want the emitter at around Supply-1V. The emitter current is about the same as the collector current so lets set Re+Re1=1V/5ma=200ohms.

We need the AC gain to be 13. As you pointed out the AC gain is approximately (Rl in parallel with RC)/Re. As @LvW has kindly pointed out the approximation is due to the transconductance of the transistor. This has the effect of reducing the effective gain. There are two ways of handing this do some complex calculations and come up with a number that is only valid for a certain set of conditions or throw in some extra gain simulate or build and adjust as needed. Lets take the second approach assume (Rl in parallel with RC)/Re = 15. This puts Re as 75ohms so Re1 is 125ohms.

The average base current is going to be 5ma/hfe(min) which is going to be around 63uA for this transistor.

As a rule of thumb the current through the base voltage divider should be about ten times this so that the base current does not mess with the voltage division to much. So lets say this current is 650uA.

The base voltage needs to be about Ve-.7 =supply-1.7 so R2 is 1.7/650ua=2.6k AND R1 is (13-1.7)/650uA=10.38k.

This approach has involved lots of "abouts" on the whole in practical design it is a much simpler and faster approach than working out every last theoretical equation. Build it or simulate it then correct it you will probably have to do that anyway.

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  • \$\begingroup\$ Thanks for the response. I just realized my instruction is to have an input source voltage of between 10mVp-p - 100mVp-p. That gives a maximum peak input voltage of 50mV. How is it possible to get an output of 1V peak if I can't exceed 50mV on the input with a gain of 13? It doesn't make sense. Am I missing something? \$\endgroup\$ – Luqmaan Jan 26 '17 at 20:55
  • \$\begingroup\$ @Lugmaan 13 always seemed like a strange number what would make more sense is a gain of 13db this corresponds to a voltage gain of 20 which would fit perfectly with 50mV-1V. \$\endgroup\$ – RoyC Jan 26 '17 at 21:31
  • \$\begingroup\$ It's not in dB. My lecturer said I have to figure it out myself. I heard students talking about using a potentiometer. How? I don't know. A multistage amplifier would work but I don't think that's the method he is looking for. \$\endgroup\$ – Luqmaan Jan 27 '17 at 16:39
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I have to assume your source impedance is \$0\:\Omega\$, since you didn't specify it. Your output impedance is specified, but while it's not entirely clear to me, if when you write "gain should be 13" and the output is \$2\:\textrm{V}_{pp}\$, that you mean loaded or unloaded by the indicated \$R_L=1728\:\Omega\$. But given that a load is specified, I lean towards a "loaded" specification. This means the BJT will be providing more gain than that. Which is a lot already, without the load. But there it is.

Not knowing what the load actually is being used for, I might recommend considering \$R_C=1.8\:\textrm{k}\Omega\$ for no other reason than maximizing power transfer to the load. But this would make the gain pretty high and I'm not willing to go there. So I'd select \$R_C=1.0\:\textrm{k}\Omega\$ as a compromise. This still means a gain of 20.5 before the loading and that's high for your topology. But it could be worse. So I'll take a shot there.

For temperature stability, I want the DC emitter bias point to be at least \$V_E=-1\:\textrm{V}\$. Given a \$13\:\textrm{V}\$ power supply span, though, I've still got some \$10\:\textrm{V}\$ of headroom for \$V_{CE_{min}}\$ and \$V_E\$. I think I'll reserve \$V_{CE_{min}}=-4\:\textrm{V}\$ and \$V_E=-2\:\textrm{V}\$. That leaves another \$7\:\textrm{V}\$ for \$\pm\$ swing span. Way more than I need.

To center the swing, I compute that the quiescent \$V_{C_Q}=-13\:\textrm{V} - \frac{-13\:\textrm{V}+2\:\textrm{V}+4\:\textrm{V}}{2}=-9.5\:\textrm{V}\$. That means \$I_{C_Q}=\frac{-13\:\textrm{V}-\left(-9.5\:\textrm{V}\right)}{R_C=1\:\textrm{k}\Omega}=-3.5\:\textrm{mA}\$. And that means that \$R_E+R_{E1}=\frac{-2\:\textrm{V}-0\:\textrm{V}}{I_{C_Q}}\approx 571 \:\Omega\$.

This needs to be split between two resistors. Since the gain needs to be about 20.5 (to get a net 13), I'll need \$R_E\approx 49\:\Omega\$. A standard value is \$R_E=47\:\Omega\$. But before I set a value here, I need to think about another factor.

A BJT has a little-re value that is about \$r_e\approx\frac{26\:\textrm{mV}}{I_{C}}\$. In this case, we use \$I_{C_Q}\$ and will get about \$7.4\:\Omega\$. That's a fair amount, considering. So I really want \$R_E=39\:\Omega\$. Given that, I may as well set \$R_{E1}=560\:\Omega\$. The new \$V_E=I_{C_Q}\cdot\left(R_E+R_{E1}+r_e\right)\approx -2.12\:\textrm{V}\$. And now I can estimate that \$V_B= V_E - 700\:\textrm{mV}\approx -2.82\:\textrm{V}\$.

The divider is pretty easy, now. We want about one tenth of the quiescent collector current to flow in \$R_1\$ and we'll assume that about one tenth of that much feeds the base (assuming \$\beta=100\$ as a conservative value.) So, \$R_1=\frac{-2.82\:\textrm{V}-\left(-13\:\textrm{V}\right)}{350\:\mu\textrm{A}}\approx 29.1\:\textrm{k}\Omega\$. Call it \$R_1=33\:\textrm{k}\Omega\$. And \$R_2=\frac{0\:\textrm{V}-\left(-2.82\:\textrm{V}\right)}{350\:\mu\textrm{A}-35\:\mu\textrm{A}}\approx 8.9\:\textrm{k}\Omega\$. Call it \$R_2=9.1\:\textrm{k}\Omega\$.

That's it:

schematic

simulate this circuit – Schematic created using CircuitLab

I think you'll find that it simulates approximately well to the design approach shown above.

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