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I need to pass a 100MHz continous clock between an MCU and FPGA. The clock edges are aligned to various interface signals between both devices. I wonder if I can pass a submultiple of the clock like 50MHz or 25MHz and use the PLL inside the FPGA to multiply the incoming slower clock to 100MHz again.
What is the phase relationship between input and output clock of a PLL when the output is a strict integer multiple of the input clock?
Distributing a submultiple of your required 100 MHz common clock should work.
A PLL will have whatever phase relationship its PSD requires for zero correction. This is typically in phase for logic based PSDs, and in quadrature for mixer type ones.
In an FPGA, the clock PLL will have many options for setting the in/out phase relationship. You will certainly have an option for an in phase lock. You will also probably have options for a little phase advance or retard, to cope with distribution delays through the clock bus, or even to offset setup/hold timing requirements of I/O latches.
The phase error (the tracking error) depends upon at least 2 things
1) the order of the control loop that performs the phase tracking
2) static and dynamic errors caused by DC and timing errors in ALL the circuits that touch the edges (the phase information) of both the Input and the Internal clocks.
I once assisted a teammate in implementing a QuadratureGenerator; the 90-degreesness was very bad; we were told "It has a sweet spot".
OK. So I did some back of the napkin math, and realized the loop-gain was 1.7, meaning the ability-to-control really did not exist. Additionally, the input signal was << 1nansecond edge, and the phase-adjustment required a slicer to select a time-of-zero-crossing, pretty much impossible on a fast edge. To function, the circuit skewed its operating point into saturation, to greatly slow the edge and allow the slicer to be effective.
Learned quite a bit about phasenoise, from that circuit.
