# How many states are possible for this ripple counter?

How many states are possible for this ripple counter ?

MY try :

If for an instance, I remove the NAND gate, then it works like a down counter.

Assume Q2Q1Q0 = 000.

Here, Preset is active high. If PR = 1, then we have to check the normal functioning of the FF otherwise output is zero.

000 -> 111 -> 010 -> 011 -> 100 -> 101...

I am not sure about its correctness. I might be wrong in the implementation of how preset works here ?

• Can you please show your reasoning? Jan 23, 2017 at 10:45
• @VladimirCravero I got these states : 000,001,010,011,100,101.But, as such I am not sure for correctness. If possible, Can you answer? Jan 23, 2017 at 10:53
• Yeah well I can answer, but I would like to understand where you got stuck. You did not show your reasoning, but your results. Edit your question adding a bit about what you did to try to solve the problem. Jan 23, 2017 at 11:08
• @VladimirCravero I'hv edited with some explaination. Can you please check now ? I might be misunderstanding the working of Preset here ? Jan 23, 2017 at 11:51
• It's active-low in the same sense that the output of the NAND gate is active-low -- it's indicated by the bubble on the symbol in the schematic diagram, as I said. Note that the clock input of each FF also has a bubble. This indicates that the FF updates on the falling edge of the clock signal. This makes the question more subtle than you might think, because now you must consider the case where the clock on the middle FF falls before its preset has been negated. Jan 23, 2017 at 12:59

It's hard to know just what your homework wants to hear, since there are at least three different answers: 2, 6 or 7.

I suspect that the desired answer is 7, but you haven't defined what a "state" is. Are states measured at the falling edge of the input clock, or are more transient conditions also counted?

First, of course, the circuit works as an up counter without the NAND, not a down counter. Until you figure out why that is so, you're going to have trouble with what follows.

Consider the counter at a state of 100, with the clock high. When the clock goes low, Q0 will toggle, and state becomes 101. When the clock goes high, the NAND is activated, and the state becomes 111. So, at a minimum the state 110 will not occur. Right?

However, now look at what occurs when the clock goes low. Q0 will go low, but it may not be able to trigger Q1 if the preset condition on Q1 has not released. The question is, what is the relative propagation delay between the flip-flop and a gate, and what is the release time for the preset WRT the clock? Keep in mind that all FF data inputs have both setup and hold time requirements, and if the preset internal logic includes a gating function to either of the JK inputs this must be taken into account.

Assuming the flip-flop has a greater propagation delay than a gate (reasonable, since a flip-flop is essentially a collection of gates), and a flip-flop can operate immediately upon release of a preset (not reasonable from first principles, absent a detailed examination of the FF internals, but probably the assumption you should make for this problem), the falling clock will produce a transition from 111 to 000, and all will be well with either 6 or 7 states allowed (101 only exists for half a clock period, but it does exist), depending on how you sample your states.

But let's say that the assumption of preset release is not met. Now a falling edge will drive state 111 to 110, as the lingering preset prevents Q1 from triggering, and the missing state is restored. However, this will obviously result in a counter with 2 states, 111 and 110. So, under this assumption, upon power-up in a random state, within 6 clocks maximum the counter will settle into a 2-state loop.

The possibility of this sort of timing glitch is the reason why ripple counters are generally a very bad idea, unless your only concern is dividing a clock by an integral power of 2. The skew conditions caused by the ripple timing can produce errors which are both subtle and disastrous.