I did a digital design in Quartus II and my board DE1-SOC FPGA, now I want to read 3 factors: general speed that digital design takes to finish the application, area of the design if it would be a real chip, or at least the area taken in the FPGA, and lastly Power, I wish to have a estimation of the power utilized by my design.

This is to compare with another design made by a schoolmate.

How can I achieve this EASILY by using tools in Quartus.

Power Estimator is available in Quartus 2, but what about SPEED?

PD: As a homework, my design pick up a list of 57.600 8 bits binary numbers (.mif), one by one, pass it through some arithmetic and output 3 sets of 57.600 8 bits binary numbers in ON-Chip RAM. Actually I don't have any proposed constraints, or frequency to achieve, I only expect it to be "standard".

I wish to read any kind of simple estimation of power, area and speed.

  • 1
    \$\begingroup\$ You will have to establish what the latency and throughput are of whatever you have designed, then scale that to the work you're trying to get it to do. What are you trying to get it to do, you don't give any of the pile of detail that needs to accompany your question. You can't do this 'easily' I'm afraid, despite writing it in big letters. The synthesis report will have already given you device logic usage and maximum clock frequency. \$\endgroup\$ – TonyM Jan 23 '17 at 12:46
  • \$\begingroup\$ Thanks TonyM, can you explain where to find that "maximun clock frecuency" in Quartus II? I'm updating my question with more details. I didn't want to extend myself too much on details, because the answer I need is mostly general that can fit any scenarios. I'm just experimenting and learning. \$\endgroup\$ – sujeto1 Jan 23 '17 at 14:25
  • 1
    \$\begingroup\$ Good for you and I do understand your approach but you'll get the best help from the crowds if you've provided a detailed question. It shows what the problem is and just how much you've tried to solve it. There are many on here who get off on writing sneering comments to undetailed questions - don't give them fuel :-) Look in the Quartus timing report section. \$\endgroup\$ – TonyM Jan 23 '17 at 14:47
  • 1
    \$\begingroup\$ Altera (now Intel) has their "PowerPlay Early power estimator" excel spreadsheet for doing the power estimation, you can feed in things like number of CLBs, switching speed, % activity and other things manually or it can take a quartus project file (i forget which) if you need more detailed power stats, although I'd assume that this functionality is built into Quartus (and if it isn't, then it should be) \$\endgroup\$ – Sam Jan 24 '17 at 6:47
  • 1
    \$\begingroup\$ Sure but first, have you simulated your design, maybe using ModelSim? As part of that, have you written a testbench for your design? If yes to these, it's straightforward to get the data processing time (something like: number of clocks to do each step x number of steps x clock period). Otherwise you need to do this equation by examining your circuit, which is also straightforward just a different method. \$\endgroup\$ – TonyM Jan 26 '17 at 7:53

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.