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I'm working on a project on spartan 6 using xilinx ISE 14.7. When I opened a schematic view, I cannot recognize the red triangle between those connections, which I think should not be an predefined block such as buffer. Is that an amplifier? If it's true, why it put in an opposite way? I'm new to fpga, thanks a lot for any help.enter image description here

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when I check the signals it shows two IOCLK as output pin and the others as input pin.

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It simply indicates that the pin connects to one bit of a bus in the schematic.

Buses (*) are indicated by a thick line, and you should notice that wherever one bit of that bus only is connected the bus goes into a triangle, and then from the triangle there is a thinner line going to the pin.

It's not a buffer, nor is it configurable. It is in fact not anything physical at all, simply how Xilinx chose to represent places where a single bit from a bus is used.


(*) Note: a bus can be only a single bit wide if for example it is declared as something like: wire [0:0] imOneBitWide;

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It probably just means it's an input. The picture below is how I normally see this in Altium. Pins 19 and 22 are inputs because of the inward arrow, and the others are either input or output because of both arrows. I'd normally expect it to be part of the component though, rather than something you add on the schematic. That's the confusing part.

It also looks a bit like a buffer symbol, so it could be just to signify that this one is the line that is buffered by the chip, and not the DIVCLK line.

enter image description here

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  • \$\begingroup\$ Hi, Cameron, thanks for the answer. I just updated another picture, it looks weird if it's input, and I confirmed in schematic it's an output pin. If it's a buffer, could it be defined by .ucf file? I checked the Verilog module didn't find any sign of buffer connected with those pins. \$\endgroup\$
    – Ziang Gao
    Jan 24 '17 at 14:23

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