A couple of questions about memory gates

Question

Let's assume I have a memory block here, I didn't set any value to it, what value would it output?
If two outputs from two different bytes meet in the same wires, what happens? I'll give an example: Byte 1: 0101 0100 Byte 2: 1001 0111
Look at the following bus:

(R1 through R5 are registers, s = set, e = enable)

Let's say we have set the enable of both R1 and R2 to 1, will the two bytes from R1 and R2 meet in the same wires? (Look at my question no.2)

Couple of notes:

This is not homework, I've been reading a book about this subject and it didn't explain that stuff.
I couldn't find anything else that explains this stuff.
I know it is suggested to divide my question into 3 questions, but since each one of them is very simple enough and each of them depends on the other questions I didn't see how to do it,

That diagram is rather bad. Are they supposed to be sharing a tri-state bus, and the "e" signal is an output enable? — pjc50, Jan 25 '17 at 15:15
@pjc50, each of them is a register, a register accepts a byte and two variables, the two variables are set and enable — ArandomUserNameEG, Jan 25 '17 at 15:40
@ArandomUserNameEG Is the book called "But How Do it Know" the diagram in that book has a very similar layout on one of the pages. — zack1544, Jan 26 '17 at 2:22
@ArandomUserNameEG ye its a good book. Once you finish reading it you can use the simulator on the book's official website to write programs for it/see how the hardware interacts when a certain instruction is executed: buthowdoitknow.com/but_how_do_it_know_cpu_model.html — zack1544, Jan 26 '17 at 22:58

pjc50 · Accepted Answer · 2017-01-25 15:18:37Z

1

Depending on the sort of memory, it could be anything: all zeroes, all ones, or random data. Some kinds of SRAM will retain contents through a short power loss.
This is not supposed to happen and will damage one or both of the conflicting outputs. Unless they're designed to avoid this problem, such as "open drain" or "open collector" outputs.
Diagram is too unclear to answer.

answered Jan 25 '17 at 15:18

pjc50

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\$\begingroup\$ What is unclear in the diagram? please tell me so I can explain anything unclear, thanks \$\endgroup\$ – ArandomUserNameEG Jan 25 '17 at 15:39
\$\begingroup\$ If you enable both outputs then you will get both outputs, there is no logic in there to prevent that. Generally two outputs active on the same signal is considered an error state and should be avoided. \$\endgroup\$ – Andrew Jan 25 '17 at 16:45
\$\begingroup\$ @andrew, thank you very much i think this question is answered \$\endgroup\$ – ArandomUserNameEG Jan 25 '17 at 16:52

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