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For the voltage divider equation to hold, the output current must be made negligible relative to the current through the resistors.

IR > 10 Iout

I often see that, for the base biasing divider:

IR = 20 IB

I suppose the same conditions must be met also with the RE and RC but cannot find any guides verifying this.

Except when the Vc is almost equal to Vce and hits Vcc and the emitter resistor is momentarily off (almost off with the negligible reverse saturation current through the base-collector diode)from the circuit; RC and (RE+Vce/Ic) form a voltage divider (counting the RE and the transistor in series as one resistor and RC the other).

I know that RC must be as lower as possible than Rout to make the output behave more like a dead end in terms of current. But I don't know the practical rule of thumb for this if any.

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Usually, the external load is coupled to the collector via a dc blocking capacitor so, this means that the nominal dc bias point at the collector is unaffected by that external load. That is noteworthy for most designs of CE amplifiers.

Now, ignoring dc conditions, a fairly accurate assumption is that the ac gain is Rc/Re. If an ac impedance is across Rc then the gain effectively lowers. So, you choose a value for Rc that swamps the external impedance and the rule of ten is fine but can easy be a rule of 1 to 1 in many designs when impedance matching is important. If you study the common emitter amp, a decent approximation to the output impedance is the collector resistor, Rc.

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  • \$\begingroup\$ Sorry, I forgot about the decoupling capacitor. But supposing we have the matching output and emitter bypass capacitors which are resonating (zero resistance for AC), and the "thing" at the output has an internal resistance Rout, then RC, RG (the resistor at the emitter bypass branch) and Rout would form a voltage divider (and a current divider also). As the common emitter is often used to amplify the signal, to achieve a higher AC voltage output, wouldn't we need to minimize the voltage dropped across RC since Vout would be equal to the sum of VRG (voltage dropped across RG) and Vce ? \$\endgroup\$ – Xynon Jan 25 '17 at 20:56
  • \$\begingroup\$ Like your previous question we discussed, you have to think about the collector as a current sink where the current is a standing dc value superimposed with an ac signal. That modulated current turns into a dc voltage superimposed with the ac signal content when it hits Rc. Another thing, forget about a capacitor across the emitter resistor because for a simple single stage amp, that capacitor brings trouble in the form of bad distortion and unpredictable amplifier gain. Forget about potential dividers too; just concentrate on the collector as a current sink. \$\endgroup\$ – Andy aka Jan 25 '17 at 21:11
  • \$\begingroup\$ So if we simply raise RC higher, the AC will have to "sink" more into the output. Thank you so much for clarification. Just one last thing: The bad distortion that the emitter bypass capacitor brings. Is it because of the uncontrolled transresistance? (emitter resistor only affects the DC on the transresistance right?) \$\endgroup\$ – Xynon Jan 26 '17 at 10:21
  • \$\begingroup\$ The collector will sink the same current (a dc part and an ac part). If Rc rises then that same current flows through a bigger resistor and therefore the collector dc and ac voltage rises (ohms law). With the emitter resistor bypassed by a capacitor, the gain is maximum and dictated by hFE (beta) and hFE varies with temperature, frequency (a bit) and no-longer is there any negative feedback hence, for anything other than pitifully small signals you get uncontrollable levels of distortion; smaller signals are cleaner but bigger signals progressively worsen. \$\endgroup\$ – Andy aka Jan 26 '17 at 11:08
  • \$\begingroup\$ If you are happy with this answer please consider formally accepting it or maybe you need clarification on something? \$\endgroup\$ – Andy aka Aug 27 '17 at 15:54

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