Whatever I searched the web I found things about differences between latches and flip-flops. I'm so new in electronics, my question is what is the difference between gates and flip-flops?
A flip-flop is a type of logic circuit. It is made up of gates. Flip-flops are generally used to store information while a gate only knows about present inputs.
Said another way, a flip-flop is a group of gates arranged such that they have memory of previous inputs.
A gate performs a logic function (AND, OR, NAND, NOR). Its output always represents the current state of its inputs.
Flip-flops are bistable storage elements. Their outputs represent the results of the inputs at some previous time.
Both latches and flops are made of more basic gates. These are NAND's, NOR's, Inverterters, Transmission gate, Tri-state elements, and possibly more depending on technology node. But both a latch and a flip flop would still be considered a logic gate (but not a single stage logic gate).
A flip flop is made of two back to back latches with opposite phase clocks, in a master-slave topology. This forms a lock-and-dam system where only on one active edge does the output of the FF change states.
Alternatively a latch is open during some transparency window w.r.t the clock. This means that the latches are typically open (transparent) during an entire half-cycle (when clock is either high or low).
See other posts which go into a bit more detail with circuits:
The basic difference between Gates and Flip-Flops is much like the difference between DNA and humans....one is defined by and subsequently built entirely from the other. Gates are the fundamental building blocks of all logic solutions and are inherently asynchronous but can be used to build synchronous (clocked) logic networks.
If you know little to nothing about digital logic and really want to learn enough to be dangerous I'd start with some basic design learning.
The problem today is that an introduction to logic is invariably on a very rapid progression from SSI (your typical SSI gate like an xx7400) to an HDL (Hardware Descriptor Language, the language used to describe logic) and rapidly becomes quite complex.
To start learning with SSI, MSI and LSI (the older and smaller logic blocks) you really need to be using a book that's 8-10 years old.
Some texts do try to modernize like Roth&Kinney Fundamentals of Logic Design but becomes somewhat harder to read in the process. (you can find this text online with a Google search "fundamentals of logic design 7th edition pdf")
My personal recommendation is books like Wakerly's Digital Design Principles and Practice which are focused on HDL as a solution, but lead you through SSI, MSI, PAL/PLD, CPLD and eventually to FPGA. It's an excellent learning resource matched to Xilinx FPGA solutions and directly to their development platform.
Again your can search online and find copies of the book.
IMO for anyone trying to learn digital design these days you need to rapidly get to using PLD/CPLD devices. They are still the only remaining opportunity to learn with DIP chips. In a few more years these may be gone forever, but today you can still get a decent number of 22V10 based PLD's in which you can build conventional gate based logic solutions.
An ideal gate and an ideal flip flop encapsulate two fundamentally different behaviors. An ideal gate has an output which will go high or low instantaneously based upon the states of the inputs. An ideal flip flop has an output which will remain at a steady value except on a rising, falling, or any edge is received on the clock input, whereupon it will instantaneously capture the state the data input had an infinitesimal amount of time before the clock edge, and will start outputting the new state an infinitesimal amount of time later.
Ideal gates provide no means of creating any sort of delay, since their outputs respond immediately to changes in their inputs. It is possible to build latching circuits out of ideal gates if the conditions necessary for latching will always be held for a finite amount of time. Building a flip flop out of ideal gates, however, is not possible because a flip flop requires an element that can delay the change in the output until after it has sampled the input and/or delay any change in the input so that it will capture the state the input had before a clock edge.
When working with real parts, the distinction between flip flops and gates is less rigid than with ideal parts, because it often takes real gates' outputs a somewhat-predictable amount of time to change in response to their inputs. This makes it possible to use gates to construct delays of the sort needed to make a flip flop work. Still, I think the distinction is a useful one because a design that uses flip flops and gates can be made to work when using any combination of parts which are at least as good as they promise to be, while a design which tries to build flip flops out of gates may fail if some gates are faster than promised but other gates are not.