# Implement AND gate multiple ways (positive & negative logic)

Could somebody explain to me how how negative and positive logic works? If I have an AND gate the truth table will be

x y z
0 0 0
0 1 0
1 0 0
1 1 1

If I wanted to implement an AND gate another way, I know i can use De'Morgans law and convert it to an OR gate while inverting all the inputs/outputs. How does this work with a NAND gate? If i invert all the inputs/outputs I would get something that isn't the truth table as an AND gate

x y z
0 0 1
0 1 0
1 0 0
1 1 0

edit: Would the NAND gate use negative logic for output and positive logic for it's input to implement it as a AND gate?

Positive logic assigns logic '1' to high voltage and logic '0' to low voltage. Negative logic does the opposite ie. logic '1' = low voltage and logic '0' = high voltage.

A truth table only tells you the logic values, not the voltages that produce them. However if you are changing from positive to negative logic then logic '1' in positive logic translates to logic '0' in negative logic. So to convert a gate from positive to negative logic you just have to invert (negate) all the signals.

For example if you had a positive logic AND gate that you wanted to use in a negative logic circuit, you would have to put inverters on both the inputs and the output. That combination is then a negative logic AND gate, and its truth table (in negative logic) is the same as the bare AND gate was in positive logic. However its truth table in positive logic has all the '1's and '0's inverted.

De Morgan's law says that an AND gate with inverted output (ie a NAND gate) is equivalent to an OR gate with inverted inputs, and an AND gate with inverted inputs is equivalent to an OR gate with inverted output (ie. a NOR gate). This is useful when for example you only have NAND gates and need to create a NOR function, or you want to reduce the number of gates in a circuit.

Applying De Morgan's law will not change positive logic into negative logic, but it helps when you want to invert a lot of signals with the minimum number of gates. So your AND gate with 3 inverters could be converted to a NOR gate with one inverter on the output - which reduces the number of gates from 4 to 2.

• Is it possible to have inputs and outputs in different logic? For instance, if I have a NAND gate, and I treat the inputs as positive logic and the output as negative logic, this will result in an AND gate? – FreeStyle4 Jan 27 '17 at 4:12
• Yes, positive/negative logic is just in your head. But it can be confusing to use different kinds of logic in one schema (write to each point, what 0V means and what 5V means just here). Usually the positive logic is used for describing the whole device and inputs active in zero are marked with negative symbol (line over name, or small circle on input). But how you see voltage level inside the device just inside your head is your problem. On the other hand mixing kinds of logic can be really confusing, so it is reason, why it is not recommended (but not forbidden). – gilhad Jan 30 '17 at 1:20
• In the end you should be clean, what does your device, when you attach 0V here and 5V there, and what voltage should be expeted as a result on this pin. Usually positive logic is used as common, but sometimes the negative can better desribe the problem. But connecting mix of positive and negative logic parts would be confusing to work with because the same IC would be NAND positive, OR negative or AND mixed this way logic. It is similar to wheather you in mathematic substract positive number or add the same negative number - result is the same, your vision differs only. – gilhad Jan 30 '17 at 1:27

With NAND gate it works the same way - you implement AND gate in the NAND gate as OR gate with both inputs and output negated, then you negate the result as NAND is AND followed by NOT gate.

NAND:
x y z
0 0 1
0 1 1
1 0 1
1 1 0

OR:
x y z
0 0 0
0 1 1
1 0 1
1 1 1

OR with both input/ouput negated (so it is AND)
x y z
1 1 1
1 0 0
0 1 0
0 0 0

OR with both input/ouput negated (so it is AND) and then negated again (so it is NAND)
x y z
1 1 0
1 0 1
0 1 1
0 0 1

so if you rearrange the last table, you get the same as NAND

The basic symbols are positive logic (positive input), while DeMorgans and the corresponding DeMorgans symbols are negative logic.

NAND: $X = \overline {A \cdot B}$ with DeMorgan's $X = \overline A + \overline B$ (Negative OR).

Two 1's input on NAND symbol will produce a 0 output. Any 0 input on DeMorgan's NAND symbol will produce a 1 output.

The truth table does not change, but the use of DeMorgans symbols places emphasis on the desired input state. Very useful for debugging, when you are not familiar with the design.

Same thing for any other gate.

AND: $X = A \cdot B$ with DeMorgan's $X = \overline {\overline A + \overline B}$ (Negative NOR).

Two 1's input will produce a 1 output. Any 0 input will produce a 0 output.