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My textbook understanding is that the source terminals (S) of the access transistors in a 6T SRAM cell are to be connected to the bit lines (BL/BLB) while the drain terminals (D) to the storage nodes (Q/QB). Now while simulating an SRAM cell in HSPICE, exchanging the Source and Drain terminal connections doesn't seem to change the output. In fact, I thought about this only after I saw some SRAM netlists available on the internet where they had connected S to Q/QB and D to BL/BLB! I get that MOSFET is a symmetrical structure and S/D can be interchanged in a standalone device, but is it true while designing a circuit?

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In IC design you can (usually) just interchange the connections of source and drain as you already point out, because it is a symmetric device.

With discrete devices a clear difference between source and drain exsists, that is because the bulk/body connection is tied to one of the pins, making it the source.

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