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I have an algorithm:

y[n] = x[n] * sum(x[0:31])

x is in the input stream, y is the output stream, both one sample per clock cycle. One condition is that the input is not contiguous, there is a valid flag that indicates that when the input is valid. The entire packet is contained in x[0:255], and generally we only get a single, infrequent packet. I'm trying to figure out what the correct logic structures are for implementing this seamlessly.

First, I thought I would just use a shift register on the input, shifting on input valid. That way I can "stall" the input flow until I have 32 sample summation. The problem I found with this was that after I received the 256 input valid flags, I still had 32 samples stuck in my shift register and no extra valid flags coming in to shift them out.

The next idea I had was to use a FIFO. The FIFO read enable line would be controlled by a flag that indicates that the summation answer is "ready", and that the input FIFO is not empty.

Am I overthinking this? Is there a simple solution for this?

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  • \$\begingroup\$ A FIFO seems to be a good solution for this case. But also the SR solution is OK. You don't need the valid in signal to keep coming if your internal logic recognizes the past valid signals and operates on the data. \$\endgroup\$ Jan 28, 2017 at 1:43

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It seems like to you want to process when there are a fixed pipeline (32) of elements available, so a shift register should work fine, and that would be the simplest way if implemented in logic cells. But 32 words can be a lot of cells, so you may instead want to implement that storage in memory. In that case, whether you call that a FIFO or shift register just depends on the in and out pointers manipulation. So this would be part of the datapath scheme.

Moving on to the control scheme, you have some description of the wanted behavior at the tail end, but not much on the front end. So I am going to ignore the front end. You want to start processing and output a word when there are 32 words, so it is natural to have a counter to count the number of words stored in the datapath (FIFO or shift register). When the counter hits 32, output starts and the the counter is kept at 32. So for the tail end, it simply means letting the counter going back down to zero before stopping.

A quite obvious way to add up the elements is to add them as they come in one words a time. When the count hits 32 and is kept at 32, add the new one while subtract the old one spilling out at the other end (I am guessing this is how you want it to work).

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A shift register forces the output timing to be locked to the input timing. Gaps in the input data valid will impose gaps in the output as well, leaving data stuck in the fixed-length pipeline as you have noted. A FIFO functions as a variable-length pipeline, allowing the output timing to be decoupled from the input timing.

FIFOs are very commonly used, and all of the FPGA vendors have tools that make it easy to configure both synchronous and asynchronous FIFOs, using either LUT RAM or block RAM, depending on the size, etc.

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