I have a problem with LPDDR2 clock period cumulative error measurement tERR(11-50per) but shorter length measurement are OK with some margin. I'm looking at some cause or tips to understand or fix this issue.
Here is a qualification test summary:
I've made additional TIE (Time Interval Error, which is cumulative jitter error) measurement on this 333.33MHz LPDDR2 clock signal over a long period of time (10µs):
What I understand from TIE time trend is that on short interval jitter can be OK but on longer period it can fail as we have some quick variation.
Here is the layout of this differential clock (100µm/200µm/100µm; 33 mm long):
FPGA Memory controller clock output is on the left and LPDDR2 is on the right. In the middle the clock goes under a flash memory chip which is only used at startup but is still powered.
My guesses are:
- Flash memory change impedance and decrease signal quality due to some crosstalk from radiated power.
- The two via on the left that make the pair not differential also decrease signal quality inducing some long term jitter.
- Jitter due to memory controller
If you have some clue to understand this issue, it would be really helpful.
Close-up screenshot of clock signal at LPDDR2 chip. This is a PoP package.
Edit 2: Clock capture
Probable reason why there are some big drops in jitter over time. May be related to software running RAM tests.