LPDDR2 clock long term jitter issue

Question

I have a problem with LPDDR2 clock period cumulative error measurement tERR(11-50per) but shorter length measurement are OK with some margin. I'm looking at some cause or tips to understand or fix this issue.

Here is a qualification test summary:

I've made additional TIE (Time Interval Error, which is cumulative jitter error) measurement on this 333.33MHz LPDDR2 clock signal over a long period of time (10µs):

What I understand from TIE time trend is that on short interval jitter can be OK but on longer period it can fail as we have some quick variation.

Here is the layout of this differential clock (100µm/200µm/100µm; 33 mm long):

FPGA Memory controller clock output is on the left and LPDDR2 is on the right. In the middle the clock goes under a flash memory chip which is only used at startup but is still powered.

My guesses are:

• Flash memory change impedance and decrease signal quality due to some crosstalk from radiated power.
• The two via on the left that make the pair not differential also decrease signal quality inducing some long term jitter.
• Jitter due to memory controller

If you have some clue to understand this issue, it would be really helpful.

Edit 1:

Close-up screenshot of clock signal at LPDDR2 chip. This is a PoP package.

Edit 2: Clock capture

Edit 3:

Probable reason why there are some big drops in jitter over time. May be related to software running RAM tests.

Answer 1

Is there any possibility that you can change your FPGA design some so that the clock for the memory comes out on pads at the periphery of the BGA pin field? If so you open up the possibility of getting a much better differential routing of the clock at the FPGA end.

You should also re-evaluate the pair of vias showing in your layout at the memory end of the diff pair. The via placement and/or routing there is not balanced.

Finally you should look closely at what the diff traces are routed over and next to. It looks like you may have an nearby copper pour that could have edge fringe coupling to one of the diff pair conductors. Ideally this clock and all the other memory control signals as a set would be routed directly over a GND plane with no plane split crossings or parallel plane edges nearby.

Answer 2

Get a FET probe, even a differential FET probe, and examine the SPECTRUM of the LVDS clock on a Spectrum Analyzer. I see some beatnotes on the Clock Waveform, where undesired energy has pushed the midpoint of rising edges to be earlier or later.

Long term jitter comes from occasional arrival of aggressor energy. Look for beatnotes. Something is causing phase-modulation. But you already know that.