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I have a problem with LPDDR2 clock period cumulative error measurement tERR(11-50per) but shorter length measurement are OK with some margin. I'm looking at some cause or tips to understand or fix this issue.

Here is a qualification test summary:

Qualification test summary

I've made additional TIE (Time Interval Error, which is cumulative jitter error) measurement on this 333.33MHz LPDDR2 clock signal over a long period of time (10µs):

enter image description here

What I understand from TIE time trend is that on short interval jitter can be OK but on longer period it can fail as we have some quick variation.

Here is the layout of this differential clock (100µm/200µm/100µm; 33 mm long):

Layout

FPGA Memory controller clock output is on the left and LPDDR2 is on the right. In the middle the clock goes under a flash memory chip which is only used at startup but is still powered.

My guesses are:

  • Flash memory change impedance and decrease signal quality due to some crosstalk from radiated power.
  • The two via on the left that make the pair not differential also decrease signal quality inducing some long term jitter.
  • Jitter due to memory controller

If you have some clue to understand this issue, it would be really helpful.

Edit 1:

Close-up screenshot of clock signal at LPDDR2 chip. This is a PoP package.

enter image description here

Edit 2: Clock capture

enter image description here

Edit 3:

Probable reason why there are some big drops in jitter over time. May be related to software running RAM tests.

enter image description here

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2 Answers 2

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Is there any possibility that you can change your FPGA design some so that the clock for the memory comes out on pads at the periphery of the BGA pin field? If so you open up the possibility of getting a much better differential routing of the clock at the FPGA end.

You should also re-evaluate the pair of vias showing in your layout at the memory end of the diff pair. The via placement and/or routing there is not balanced.

Finally you should look closely at what the diff traces are routed over and next to. It looks like you may have an nearby copper pour that could have edge fringe coupling to one of the diff pair conductors. Ideally this clock and all the other memory control signals as a set would be routed directly over a GND plane with no plane split crossings or parallel plane edges nearby.

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  • \$\begingroup\$ The memory controller is a hard memory controller with fixed pins so it's not possible to change clock output pins. I'm looking at the possibility to remove two vias on the left to improve differential signaling. I could increase the right side pair length a bit to have a closer length match but I'm within specs. Nearby copper pour is GND but yeah it can be a cause as there is only 150µm isolation, I have a new layout coming so I'll increase GND to diff pair isolation. Finally this is TOP layer and layer 2 is GND so no plane split, high-speed signaling layout rules are observed. \$\endgroup\$
    – zeqL
    Commented Jan 29, 2017 at 12:54
  • \$\begingroup\$ @zeqL - You are fighting a problem and so you should strive to make everything as perfect as possible. Saying that "I'm within specs" may not be good enough. Those via's on the right should be as close together as possible. \$\endgroup\$ Commented Jan 29, 2017 at 13:02
  • \$\begingroup\$ What I meant by "within specs" was about clock trace length. CKp / CKn difference is 500µm which mean around 3-4ps skew. All my LPDDR2 automatic qualification is OK but this tERR(11-50ps) so I'm wondering what can cause a long term jitter. GND shape close to diff seems a good candidate. Also this is a very hairy project as we don't have much space to route. I've edited my question with an additional screenshot of layout, You'll see that I can only do a slight improvement, and it will be done if I can (isolation rules). \$\endgroup\$
    – zeqL
    Commented Jan 29, 2017 at 13:21
  • \$\begingroup\$ @zeqL - In my book matching via symmetry on diff traces is very important. Vias represent an impedance inflection point and imbalance will exhibit different behavior in the two traces. \$\endgroup\$ Commented Jan 29, 2017 at 13:29
  • \$\begingroup\$ I know and in my book too it's important (Eric Bogatin's book is my bedside book) but theory and what you can do in practise is not the same. I'll see if I can make left side symetrical but I've DFM rules to follow. I've added a clock signal capture taken at LPDDR2 vias (non-symetrical ones) \$\endgroup\$
    – zeqL
    Commented Jan 29, 2017 at 13:41
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Get a FET probe, even a differential FET probe, and examine the SPECTRUM of the LVDS clock on a Spectrum Analyzer. I see some beatnotes on the Clock Waveform, where undesired energy has pushed the midpoint of rising edges to be earlier or later.

Long term jitter comes from occasional arrival of aggressor energy. Look for beatnotes. Something is causing phase-modulation. But you already know that.

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  • \$\begingroup\$ I haven't thought of spectrum analyzer. I've done some capture but nothing obvious (I was using a diff probe with the spectrum analyzer software of the oscilloscope). But I captured a long period of clock signal and I think the issue may be also software related, I need to do some test to confirm it. I added a capture on main post (edit 3) and you can see the high level voltage take around 150mV for some time, so this may explain big drops in jitter time trend. \$\endgroup\$
    – zeqL
    Commented Feb 1, 2017 at 20:07

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