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I have used TI filter tool design to make sallen key low pass filter, their are four op-amps stages. But filter tools has not calculated AC coupling capacitor that has to be included after every stage. We are amplifying audio signal hence both positive and negative cycle needs amplification. Otherwise the DC voltage that is being generated after every stage will make the amplification unsymmetrical. (Schematic is attached below)

Do we have to manually insert AC coupling capacitor or their is provision in the filter design software which I am unaware of.

Regards, enter image description here

Edit: After reading the comments, I have done changes in the circuit. Then I performed simulation in the Multisim. I am simulating only first stage of the circuit. And it is working according to the design. Can anyone please explain adding 100K ohm resistor between inverting and non inverting terminal is solving the problem. In my previous design I have made inverting amplifier using single supply, but V/2 (DC bias) was only given to non-inverting terminal of the op-amp. I was applying same logic for salley key configuration

Sallen key configuration

enter image description here

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  • \$\begingroup\$ If you would use unity-gain Sallen-Key stages, it would not be necessary to use coupling capacitors. More than that, only the first stage would require the necessary half-voltage input DC biasing. \$\endgroup\$ – LvW Jan 30 '17 at 8:43
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    \$\begingroup\$ You are NOT "adding 100K ohm resistor between inverting and non inverting terminal" You are connecting V1 to C1 to 1.65V to give Vin+ the same CM input voltage as R1. (ignoring Iin bias current errors) \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Feb 20 '17 at 20:43
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When using single-supply op amps for AC amplification such as filters, it is necessary to provide an offset voltage, since a single-supply amp is incapable of providing a negative signal. Ordinarily this is done by generating a pseudo-ground about halfway between ground and the power supply voltage. For a low-pass filter which is intended to reject all AC signals and only pass the DC component this may not be necessary, or if the signal has an appropriate offset which allows operation on the AC component.

I've not bothered to analyze your filter sections, but if the low-frequency gain is greater than one, the cascaded gain may well give you trouble. However, you cannot simply add blocking caps between stages unless you provide a pseudoground to reference each section's signal to. Furthermore, since there is no DC path in the non-inverting branch of the filter, adding a blocking cap will cause the simulator to barf, and a real circuit will drift to one saturation level or the other.

So, no, you cannot simply add blocking caps.

Furthermore, any blocking cap will add a high-pass component to the filter, and so it will be characterized as a band-pass filter.

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Your DC gain is only 2 per stage so only the input and output need AC coupling.

Choose C from =1/(2pi * f *R) for the output load and input R values then DC bias for input. e.g. 100K

enter image description here

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  • \$\begingroup\$ I did online simulation after doing the changes that you have done. It is working as per the design. Can you explain the logic of connecting V/2 (Vcm1) to both inverting and non-inverting terminal and connecting resistor between the two. In my previous design I have made inverting amplifier using single supply, but V/2 (DC bias) was only given to non-inverting terminal of the op-amp. I was applying same logic for salley key configuration. \$\endgroup\$ – TapasX Jan 31 '17 at 6:39
  • \$\begingroup\$ both inputs must have DC input to Vcc/2 to be inside Vcm range and 0V differential for output to stay in linear range \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 31 '17 at 8:18
  • \$\begingroup\$ There are four stages each of which has a gain of 2. Do I have to connect AC coupling capacitor between each stage also or just between input and output as you have done. \$\endgroup\$ – TapasX Feb 20 '17 at 10:39
  • \$\begingroup\$ Why each stage? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Feb 20 '17 at 20:38
  • \$\begingroup\$ I think a Lowpass, Multiple Feedback, Bessel would perform much better for group delay, Td with no peak unlike 2x Td at cutoff f for 8th order Butterworth. It would be a flat Td. Why dont you define ALL the specs 1st, then design it? e.g. Sensor input , Vcm gain, passband ripple, CMRR. bandstop rejection, Td Vcc Vee sig source & output range etc \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Feb 20 '17 at 21:04
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The design you show there is not really large enough to see well.

I can see that each stage has a gain of more than 1 so any DC at the input will be amplified. In that case you will need isolate each stage with a coupling capacitor and provide DC bias for each stage.

You can probably reduce the number of components required by just putting a series capacitor at the input together with two resistors to provide half-rail biasing. Then if you put a capacitor in series with the bottom of the gain defining resistors each stage can take the bias from the previous stage. (I can't read the ref designator).

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That's what Vcm is for. Set it to mid rail.

Now either use it to reference your input and output, or, AC couple input and output.

With a decoupling capacitor, a factor of 10 is sufficient. Set its RC -3dB frequency a factor of 10 lower than the lowest audio you want to pass through the filter.

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Hmm, Low pass implies DC coupling.

In audio work that is usually not needed so you could add decoupling capacitors.

Given each stage has 2x gain then you have maximum 16x input off-set error of first stage. With interstage decoupling your amplified error would be 2x last stage off-set error only or none with a final output capacitor.

I would consider an input cap and one in the middle large enough to cover your desired low frequency cut-off given the feedback network impedance. This would result in a maximum of 4x the off-set error and a capacitor free direct DC output coupling.

Selecting high quality op-amps and resistors might be another alternative to keep the 16x off-set error within workable limits across temperature and supply variations.

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