Is making a D flip flop with asynchronous level triggered reset possible?

Question

I am starting to learn verilog coding in college and didn't have that much of a problem till now. I think I have the basics down perfectly. But I just hit a brick wall with this one. I was experimenting with behavioral modeling and ended up having this problem.

It is easy to make a D flip flop with synchronous level triggered reset like this

always @(posedge clk)
begin
    if(clr) begin
        q <= 1'b0;
    end
    else begin
        q <= d;
    end
end

Or making a D flip flop with synchronous edge triggered reset like this

always @(posedge clk or posedge clr)
begin
    if(clr) begin
        q <= 1'b0;
    end
    else begin
        q <= d;
    end
end

But how can I make a level triggered but asynchronous reset? I cannot do

always @(posedge clk or clr)

because that would be oring two incompatible types, so an error will be thrown while doing the RTL synthesis. I cannot do

always @(posedge clk)
begin
    q <= d;
end

always @(clr)
begin
    q <= 1'b0;
end

since that would require multiple sources to drive q, again problem at RTL synthesis.

So my question is, is making a D-flip flop with asynchronous level triggered reset possible or not? Both in verilog and in digital logic.

Answer 1

Here's Xilinx's example of a "Flip-Flop with Negative Edge Clock and Asynchronous Reset":

always @(negedge C or posedge CLR)
    begin
        if (CLR)
            Q <= 1’b0;
        else
            Q <= D;
    end

(Source: Synthesis and Simulation Design Guide, UG626, Oct 19, 2011)

Notice that this is basically the same as your second example (except using the opposite clock edge). And in fact this is a level-sensitive clear, not an edge-sensitive clear, because if clear is held high, the output will continue to be held low, even if new clock edges arrive and/or the D input changes.

Answer 2

I'm not terribly familiar with Verilog, but by my understanding some synthesis tools will squawk at attempts to generate synthesize synchronous and asynchronous logic on hardware platforms whose primitives do not support such things. It is possible to produce a circuit which will behave like an async-reset flip flop, provided that reset edges don't occur near clock edges. Here is an example. An important thing to note with this circuit, however, is that while a hardware asynchronous reset is guaranteed to clear any metastability, a circuit which simulates one offers no such guarantee.

Answer 3

Not sure of verilog but in VHDL I thought it would be something like this:

ARCHITECTURE behavioral OF dff_asynch IS 
BEGIN  
 PROCESS(D, Clk, Clr, Pre) 
 BEGIN 
  IF Clr = '0' THEN  -- Don’t wait for clock 
   Q <= '0'; 
   Qbar <= '1'; 
  ELSIF Pre = '0' THEN 
   Q <= '1'; 
   Qbar <= '0'; 
  ELSIF (Clk'event) AND (Clk='1') THEN   -- Positive Edge 
   Q <= D; 
   Qbar <= not D; 
  END IF; 
 END PROCES

Answer 4

1) None-reset: always @(negedge C) begin Q <= D; end

2) Synchronous reset always @(negedge C) begin if (CLR) // If C is not running, a change in CLR doesn't affect Q Q <= 1’b0; else Q <= D; end

3) Asynchronous reset always @(negedge C or posedge CLR) begin if (CLR) Q <= 1’b0; else Q <= D; end