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I am starting to learn verilog coding in college and didn't have that much of a problem till now. I think I have the basics down perfectly. But I just hit a brick wall with this one. I was experimenting with behavioral modeling and ended up having this problem.

It is easy to make a D flip flop with synchronous level triggered reset like this

always @(posedge clk)
begin
    if(clr) begin
        q <= 1'b0;
    end
    else begin
        q <= d;
    end
end

Or making a D flip flop with synchronous edge triggered reset like this

always @(posedge clk or posedge clr)
begin
    if(clr) begin
        q <= 1'b0;
    end
    else begin
        q <= d;
    end
end

But how can I make a level triggered but asynchronous reset? I cannot do

always @(posedge clk or clr)

because that would be oring two incompatible types, so an error will be thrown while doing the RTL synthesis. I cannot do

always @(posedge clk)
begin
    q <= d;
end

always @(clr)
begin
    q <= 1'b0;
end

since that would require multiple sources to drive q, again problem at RTL synthesis.

So my question is, is making a D-flip flop with asynchronous level triggered reset possible or not? Both in verilog and in digital logic.

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4 Answers 4

Reset to default
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Here's Xilinx's example of a "Flip-Flop with Negative Edge Clock and Asynchronous Reset": 

always @(negedge C or posedge CLR)
    begin
        if (CLR)
            Q <= 1’b0;
        else
            Q <= D;
    end

(Source: Synthesis and Simulation Design Guide, UG626, Oct 19, 2011)

Notice that this is basically the same as your second example (except using the opposite clock edge). And in fact this is a level-sensitive clear, not an edge-sensitive clear, because if clear is held high, the output will continue to be held low, even if new clock edges arrive and/or the D input changes.

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  • \$\begingroup\$ Does such a spec, written as above, provide any indication about whether the circuit is required to avoid output glitches or weird behavior if malformed clock or reset pulses arrive while D and Q are both zero? A hardware flip flop primitive which included an async reset would naturally have no trouble with such things, but avoiding such problems when synthesizing an async-reset flop out of other primitives would require extra circuitry. \$\endgroup\$
    – supercat
    May 21, 2013 at 17:31
  • \$\begingroup\$ @supercat, No, nothing in Verilog ever tells you what happens if the input signals are not at valid logic levels, for example. But, if your synthesis tool is any good, and there is such a thing available in your architecture (like in a Xilinx FPGA) the code written here will synthesize to a hardware flip-flop with asyncronous reset, not to a flip-flop constructed out of gates. In fact this is exactly the code Xilinx recommends if you want to synthesize a hardware flip-flop. \$\endgroup\$
    – The Photon
    May 21, 2013 at 17:43
  • \$\begingroup\$ If the hardware which connects to a device might output signals with invalid logic levels or timings in cases which "shouldn't" matter, is there any way to specify that a device must ignore such inputs? For example, if a board had a 74HC74 and an FPGA with some spare pins, and one wanted to absorb the function of the 74HC74 into the FPGA, and if the circuitry which drove the 74HC74 would sometimes output runt pulses on the set or reset line in cases where the output was already the correct state, could one specify that the synthesizer must produce something that would work correctly? \$\endgroup\$
    – supercat
    May 21, 2013 at 19:41
  • \$\begingroup\$ Even if some parts have both primitive flops with both async-set and async-clear, some only have one async input. If there wasn't an async-set-clear flop primitive, one could synthesize one using use an async-clear flop to track whether the last meaningful event was a clock or an async signal, and feed that into a mux along with the last clocked bit and indicator whether "set" or "clear" was active last, but such an implementation could fail if a there was a clean async reset/release, followed by a clean "1" clocked in, followed by a runt async set, even though a 74HC74 would have no problem. \$\endgroup\$
    – supercat
    May 21, 2013 at 19:46
  • \$\begingroup\$ @supercat, Verilog is a purely digital tool. The Verilog language has no concept of invalid logic levels (there are "don't care" and "high-impedance" symbols, but they don't solve your problem). It's the job of the logic cell designer to determine the behavior for invalid inputs if that's needed. That kind of work would probably be done with a SPICE-like simulator, not with Verilog. \$\endgroup\$
    – The Photon
    May 21, 2013 at 20:42
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I'm not terribly familiar with Verilog, but by my understanding some synthesis tools will squawk at attempts to generate synthesize synchronous and asynchronous logic on hardware platforms whose primitives do not support such things. It is possible to produce a circuit which will behave like an async-reset flip flop, provided that reset edges don't occur near clock edges. Here is an example. An important thing to note with this circuit, however, is that while a hardware asynchronous reset is guaranteed to clear any metastability, a circuit which simulates one offers no such guarantee.

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Not sure of verilog but in VHDL I thought it would be something like this:

ARCHITECTURE behavioral OF dff_asynch IS 
BEGIN  
 PROCESS(D, Clk, Clr, Pre) 
 BEGIN 
  IF Clr = '0' THEN  -- Don’t wait for clock 
   Q <= '0'; 
   Qbar <= '1'; 
  ELSIF Pre = '0' THEN 
   Q <= '1'; 
   Qbar <= '0'; 
  ELSIF (Clk'event) AND (Clk='1') THEN   -- Positive Edge 
   Q <= D; 
   Qbar <= not D; 
  END IF; 
 END PROCES
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1) None-reset: always @(negedge C) begin Q <= D; end

2) Synchronous reset always @(negedge C) begin if (CLR) // If C is not running, a change in CLR doesn't affect Q Q <= 1’b0; else Q <= D; end

3) Asynchronous reset always @(negedge C or posedge CLR) begin if (CLR) Q <= 1’b0; else Q <= D; end

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