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I've looked around for the answer to this question, so I'll only ask the new questions.

I am designing a PC board that has some need for circuits carrying 2 amps and some that are very low power micro-controller (micro-amp) circuits.

I want to use a 4 layer circuit board. The board house I want to use supplies boards with 1oz copper on the top and bottom layers and 1/2oz copper on the inner layers.

My board has a lot of surface mount components, and a small amount of through hole components.

There are DC-DC buck and boost converters on the board, operating around 1 - 2 Mhz (using shielded inductors). There is a microcontroller running a 20mhz crystal as well as a 32.768khz crystal and a USB connector. That's about as fast as my circuit gets.

I am mounting my board into a grounded cast aluminum box to avoid noise.

I see a lot of texts recommending me to use my top layer for power buses and the bottom layer for ground. They say to use the inner two layers for signal routing and low current needs.

I am guessing that is to also provide some noise suppression for the faster circuity in the inner layers.

Because my board and components are fairly dense, (1000+ pins in DipTrace in 4 x 3 inch board) and because they are mostly surface mount components, my question is that I'm finding it easier (and my plan) to route small signal traces on the top layer layer, high speed signal traces on the 3rd (from the top) layer, and use the 2nd layer for Power and the bottom one for ground. I have no high current ground circuits. All of the high current circuits I have are Power circuits.

Is doing this OK or will I run into gotchas (like needing to make sure the traces on the power circuits are double wide because the 1/2oz copper)

And would it be smarter to use the 2nd layer for ground and the bottom (1oz copper) for power? I don't think I need the shielding of the ground being on the bottom since my entire board will be going into the metallic enclosure which will also be ground.

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  • \$\begingroup\$ I am not sure where did you get these recommendations. They might be good for 8-10-12 layer boards with buried/blind vias, but not for 4-layer. The typical 4-layer setup is to use upper layer for high-speed signaling (no vias from component to component), 2-nd layer as entire ground, 3-rd layer for split power planes, and bottom for anything else. \$\endgroup\$ – Ale..chenski Feb 1 '17 at 20:07
  • \$\begingroup\$ Quick aside: You have "high current power circuits", but "no high current ground circuits"? So your high current returns are independent from ground? \$\endgroup\$ – ndim Feb 1 '17 at 20:22
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    \$\begingroup\$ Yes, high current returns are independent from ground. They use high-side MOSFET-style drivers. \$\endgroup\$ – mark b Feb 1 '17 at 20:51
  • \$\begingroup\$ @ndim For example, power switchers do have local high-current loops, so it is advisable to route these loops locally-isolated from common ground, and connect the local ground of the switcher layout through one-two vias. I am not sure however what mark b means under high-side switches and no return ground. \$\endgroup\$ – Ale..chenski Feb 1 '17 at 22:14
  • \$\begingroup\$ the switchers in this case only charge a supercap, and another one provides power for 10 or so ICs, a microcontroller, etc. The higher power circuits are kept far away and are only high-side switches that switch a +12v supply at around 10a total into 8 or 9 separate pins to go out to incandescent lamps that are grounded outside of my circuit board. So this 10a does not flow through the ground planes of my circuit. \$\endgroup\$ – mark b Feb 1 '17 at 22:19
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You will hate yourself when it comes to board bring up if you have all the important stuff on a buried layer, it makes both probing and the addition of roach wires much harder then it needs to be.

The standard stackup for 4 layers that nearly everyone goes with is signals on the outer layers, ground on L2 and power (and possibly non critical signals on L3), note that the fast stuff then ends up on L1 with the silicon (Hence no vias in high speed nets), you cannot route it on L4 unless you can organise a local reference plane under that bit of board on L3 plus appropriate stitching.

I would note that reference planes do not need to be ground, a well decoupled power plane is as good, but remember to get decoupling where the signal changes reference planes.

Buried signal layers make sense once you get to about 8 layers, but on a 4 layer?. One comment I would make is that thinner layer to layer spacing between the ground and high speed layer (whatever one it is) is a huge win both from an EMC and a SI perspective (It also makes your controlled impedance traces thinner), find out what your board house can do here.

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I have done a few 4 layer boards in the past and from experience, I would never put any traces in the inner layers. I would keep top-layer for signal traces and maybe power traces if you have enough room for them. The second layer should be your ground or split power plane. The third layer is split power plane or ground. And the fourth layer should be for traces jump (vias) and few components if you do not have room.

Here is a picture of the stackup you would typically see:

enter image description here

With this in mind, there are also a few more things to consider. For example, you should never put signal trace to close or under your oscillator as it may affect the integrity of the signal. Also watch how many vias you would need if you want to jump layers for high power traces. Just a couple things to consider along with the rest of the Design Rule Check.

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