Distance between SPI traces to prevent cross talk

I'm wondering, what is the rule of thumb regarding the distance between the SPI bus (MISO,MOSI,CLK,nCS). How to make sure there is no cross talk from one trace to other trace?

I guess the frequency is playing a role here?

• as a general rule of thumb make the traces as short as possible if the operating frequency is higher
– Raj
Feb 2, 2017 at 7:51
• Hi, thank you.. I'm asking about the distance between them Feb 2, 2017 at 7:55
• separate tracks that carry opposite signals, which cause interferences, you can have CLK, MISO running in parallel with normal distance, but have some distance between MISO and MOSI, avoid loops, make it straight as possible
– Raj
Feb 2, 2017 at 8:01
• Most important- make sure clock is clean and has no overshoot. Even consider terminating it nicely. Other signals may have some crosstalk, it's fine. What's important is that signals are stable when clock rises or falls. This is because if you have ringing on clock, shift register may shift too many times.
– user76844
Feb 2, 2017 at 16:16
• you'd have to have pretty low voltage system (1.8V, 1.2V) and extremely bad layout/massive trace lengths to get any cross-talk with enough magnitude to cause a logical error in the SPI comms Feb 4, 2017 at 1:52

The main source of crosstalk will presumably be capacitive coupling between the traces (though see analogsystemrf's answer for an analysis of inductive coupling). Suppose we have a pair of traces, 0.1 mm apart (which is about the closest you'll find on a standard PCB) and 35 μm thick (i.e. 1 oz copper). This calculator claims that the resulting capacitance will be about 1.2 pF for a 10 cm trace.

Suppose you run the SPI bus at 24 MHz. At this frequency, the capacitor will have an impedance of $\frac{1}{2\pi\cdot f\cdot C} \approx 5.5~\text{k}\Omega$. However, a square wave has harmonics, multiples of the base frequency. An ideal square wave has only odd harmonics, and can be represented as $$\sum_{k=1}^\infty \frac{1}{2k-1}\sin\big((2k-1)\cdot\omega t\big)$$ In practice, you can get a decent square wave with only through the fifth harmonic, $$\sin(\omega t) + \frac{1}{3}\sin(3\omega t) + \frac{1}{5}\sin(5\omega t)$$ At the higher frequencies, the impedance of the capacitor will be proportionately lower, but the voltage of those harmonics is also proportionately lower, so each sinusoid contributes about equally to the crosstalk.

Compare the impedance of the capacitor at the fundamental frequency to the approximately 50 Ω output impedance of a microcontroller GPIO pin, and we can see that there is attenuation of about a factor of 110. With contributions from the fundamental, third, and fifth harmonics, the crosstalk is about a factor of about 36 below the signal.

To be able to make the approximation that we only care about the fifth harmonic and below, we need to make sure that the signal is bandwidth-limited, which requires low-pass filtering. The inherent capacitance of the traces and input pin is maybe 12 pF, which with the 50 Ω driver impedance forms a low pass filter with a -3db frequency of $\frac{1}{2\pi\cdot R\cdot C} \approx 265~\text{MHz}$. This is a bit high to cut off the seventh harmonic of 168 MHz, so you can add a bit more resistance or capacitance to the trace if crosstalk becomes a problem, though I'd be surprised if it does at these frequencies and distances.

• Not even fifth harmony? At 100MHz it's roughly 1k. Also, what about inductive coupling?
– user76844
Feb 2, 2017 at 16:12
• @GregoryKornblum I've added some discussion of harmonics. Feb 3, 2017 at 20:29

[edit: reduced spacing from 0.1meter to 0.0015m (1/16" inch); crosstalk rose from 0.06volt to 4 volts] Lets examine the worst-case magnetic coupling. Use the straight-wire transmitter, coupling into adjacent-wire-over-plane receiver where the length $\cdot$ height defines the loop area.

$$V_{induce} = L \cdot \frac{di}{dt} \\ L = \mu N^2 \cdot \frac{A}{l} = \mu_0 \mu_r \frac{Area}{2\pi \cdot Distance} \\ \Rightarrow V_{induce} = \mu_0 \mu_r \cdot \frac{Area}{2\pi\cdot Distance } \cdot \frac{di}{dt}$$

Assume 0.1meter run, and 1.5mm (1/16"inch) height. [edit: Assume aggressor-victim spacing of 1.5mm.]

What is $di/dt$?

Let's assume a 100pF load (numerous ICs on one SPI clock or data line). Further assume a 1 ns slope, with $i = C \cdot dV_C/dt$, the peak $i$ is 100mA=0.1A, rising in half the edge time i.e. 0.5 ns. Thus $di/dt=0.2 A/ns$.

What is the induced voltage?

With $\mu_0=4\pi 10^{-7}$, the $\pi$ will cancel, leaving

\begin{align} V_{induce} &= \mu_0 \mu_r \cdot \frac{Area}{2\pi\cdot Distance } \cdot \frac{di}{dt} \\ &= 2\cdot 10^{-7} \cdot \frac{Area}{Distance} \cdot \frac{0.2A}{ns} \\ &= 2\cdot 10^{-7} \cdot \frac{0.1 \cdot 0.0015}{0.0015} \cdot 0.2 \cdot 10^9 \\ &= 2\cdot 10^{-7} \cdot 0.1 \cdot 0.2 \cdot 10^9 \\ &= 10 \cdot 0.4 \\ &= 4 volts \end{align}

Summary: heavy capacitive loads cause heavy transient currents, causing large crosstalk

If you Google "pcb design crosstalk" you can get a lot of results.

Anyway, some rules you should follow:

• Keep traces as short and same length as possible
• Avoid turns (90°, 45° mitter or fillet) and vias if possible
• Keep at least 2 times the required trace width between crosstalk-potential-traces.
• Placing a ground plane between traces (for shielding purposes) may also improve the performance (Keep ground plane as close to the trace as possible)