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I am working with am ARM Cortex M3 where two GPIO pins are configured as Alternate Function for use as USART pins. When setting the pins as Alternate Function, I have to set the Output Speed of those pins. (I set them at 50Mhz.)

Reading the reference manual (available here) on pages 613 and following, the baud rate of the USART seems to only depend on the APB1 clock rate f_CK.

Does the set GPIO speed influence the USART baud rate?

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  • \$\begingroup\$ Which microcontroller do you have? ARM Cortex M3 is the core, which doesn't say anything about GPIO. \$\endgroup\$
    – starblue
    Commented Mar 20, 2012 at 21:17
  • \$\begingroup\$ It's an STM32F2. \$\endgroup\$
    – Randomblue
    Commented Mar 20, 2012 at 22:36

3 Answers 3

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From what I understand, output speed is the update rate of the output. As long as it is reasonably higher than the the rate at which your output changes, it shouldn't matter too much.

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  • \$\begingroup\$ Might be worth noting you end up creating fun situations if you set it much higher then needed as you can cause oscillations and EMI by having high speed signals without termination. \$\endgroup\$
    – Kortuk
    Commented Mar 20, 2012 at 17:06
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Take a look at the architecture of your proccesor. For this purpose I use the LPC1769, but is very similar on other proccesors.

On this platform the proccesor is not directly connected to peripherals. The proccesor, as with DMA, Ethernet, USB, RAM and ROM run on it's own AHB matrix. This matrix contains connections to several high-speed peripherals on the proccesor. For example, the proccesor connects directly to the SRAM. The DMA does as well, so the CPU can handle instructions and the DMA can (on the background) move or read data from/to peripherals.

The general purpose peripherals like SPI, UART, ADC, PWM, etc. are on a seperate peripheral bus (APB). There is a bridge between the high-speed matrix and this bus. This will cause delays in data-transfer (because the bus may be busy).

In case of the LPC1769, there are 4 High Speed GPIO pins. If the state of these are changed, it wil; take immediate effect. This allows, theoretically, an update speed of over the CPU clock frequency.

You say that the max. update speed depends on the APB1 clock rate. The APB1 clock rate is the clock rate of all peripherals on group 1, which may be GPIO and UART. This clock is usually lower than the CPU, to save power.

The GPIO update speed and UART are not dependant on each other, but dependant on the clock rate of the peripherals and the AHB/APB structure.

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In many cases, the "output speed" setting of a pin controls the slew rate. The manufacturer typically does not specify the exact behavior of the device with different settings, but instead specifies that:

  1. At any particular setting, the output slew rate will be at least fast enough to accommodate a square wave output of a particular speed.
  2. Specifying a slower speed setting will result in a slower slew rate, though the manufacturer typically won't specify exactly how much, or what the wave shape will be.

Specifying a faster slew rate will cause the output voltage to switch more quickly between VDD and ground. This will generally increase peak loads on VDD, RF emissions, and the occurrence of ringing, overshoot, and other nasty effects on the output line being switched. If it's important that a downstream device see an output switch within 10ns of when the ARM commands it, then one must specify the fastest data rate and deal with the consequences. If the output is being used to control a relay that's going to switch maybe twice a second, one should use the slowest output speed, but it probably won't matter; the relay won't care about ringing, and an output that's switching a couple times per second isn't apt to cause excess RF emissions no matter how quick the edges are.

The time slow output speeds are most useful are when one is generating a signal which changes frequently, but not insanely fast (e.g. 100KHz-1MHz) or one is driving a device which will may quickly to transients in the output signal but one isn't actually sending pulses nearly as fast as the device could respond. Sending a 1MHz square wave with edges fast enough to accommodate a 50MHz wave would generate a really big amount of RF at 3MHz, 5MHz, 7MHz, and other odd harmonics of 1MHz. Slowing down the edges could greatly reduce the levels of RF noise generated. An output transition (e.g. high-low) which is sent with very rapid edges may be received with a brief "bounce" (e.g. registering as high-low-high-low). If the receiving device is fast enough to register that high-low-high-low as multiple events, that could cause trouble. Slowing down the rate at which the output switches will substantially reduce the extent to which it bounces.

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