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schematic

simulate this circuit – Schematic created using CircuitLab

Why does the voltage divider in second circuit (middle) has no impact? Vo is always equal to V4(correct me if am wrong).

And once a capacitor is introduced before the voltage divider, the voltage divider comes back into picture. I do see, that everywhere they say that capacitor does not allow DC to pass through.But how can we correlate with this circuit?

During the absence of the capacitor, does the 6V from voltage divider flow through the Signal generator? But the Signal generator itself generates voltage, then how can this oppose the flow of a Signal generator? I need a clear and elaborate explanation of this weird role played by this coupling capacitor.

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Roughly speaking, your schematics can be reduced as follows. The top schematic is as you laid them out (with just a little less "dross" to confuse things.) The schematic below each is the equivalent, reduced version using a Thevenin equivalent for your resistor divider.

schematic

simulate this circuit – Schematic created using CircuitLab

It's a little more obvious, now.

Circuit 1, of course, exhibits \$6\:\textrm{V}\$ when the output is unloaded. The Thevenin source voltage simply appears at the output, since there is no current in the Thevenin resistor.

Circuit 2 will track \$V_4\$, also for obvious reasons. \$V_4\$ is directly driving the output. The \$6\:\textrm{V}\$ Thevenin source voltage is behind a \$5\:\textrm{k}\Omega\$ resistor and can't interfere.

Circuit 3 isn't really much more complex. Capacitor \$C_1\$ charges up to the Thevenin voltage of \$6\:\textrm{V}\$ (given time) and after that the voltage of \$V_8\$ is simply jacked up by \$C_1\$'s voltage. So if \$V_8\$ is \$0\pm 1\:\textrm{V}\$, then after \$C_1\$ the voltage is \$6\pm 1\:\textrm{V}\$.

The only question really is how it is that \$C_1\$ gets that voltage. It does, because \$V_8\$ averages \$0\:\textrm{V}\$ over time and since there is a \$6\:\textrm{V}\$ Thevenin voltage behind \$R_{TH}\$, \$C_1\$ will charge up to the average of the difference. Once it does that, as \$V_8\$ rises up a little, then there will be some current flowing from \$C_1\$ back to the Thevenin voltage, and as \$V_8\$ falls below a little, then there will be some current flowing from the Thevenin voltage back to \$C_1\$. But once \$C_1\$ reaches a mean value of \$6\:\textrm{V}\$, the amount of charge leaving \$C_1\$ in one half of the cycle will exactly equal the amount of charge returning to \$C_1\$ in the other half of the cycle. And then everything is in equilibrium.


Another way of viewing Circuit 3 is that \$R_{11}\$ and \$R_{12}\$ form a voltage divider with \$6\:\textrm{V}\$ in the center and that \$C_1\$ will develop a voltage across it equal to the average difference. It charges up for a bit, while that happens, and so for a short time (several times the \$C_1\cdot R_{TH}\$ time constant) there will be an imbalance. But that imbalance will be just what's needed to charge up the capacitor until it reaches that equilibrium point where the charge leaving equals the charge arriving and the mean value then no longer changes.

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  • \$\begingroup\$ Almost complete. In circuit #2, V4 absorbs current from the +12v source through R3. R4 does nothing here except suck current from V4. \$\endgroup\$ – glen_geek Feb 4 '17 at 15:33
  • \$\begingroup\$ @glen_geek I'm just showing equivalent forms so the OP can see it "differently." Did I make a mistake? Or do you dislike my use of "can't interfere?" (I meant that solely from the output point of view.) \$\endgroup\$ – jonk Feb 4 '17 at 16:45
  • \$\begingroup\$ We both agree that OP is correct regarding Cct #2: V4 dominates entirely. I might argue that Thevenin model is 12v + 10k (instead of your 6v + 5k). Same external result, because V4 dominates. The only quibble is about current flow inside a black box...suppose V4 has a DC offset in Cct #2? \$\endgroup\$ – glen_geek Feb 4 '17 at 17:12
  • \$\begingroup\$ @glen_geek I guess I don't care about current flow inside the black box. It's enough to show that there is a resistance present which allows \$V_4\$ to drive the output, unhindered. And I think discussing the rest would have complicated things to the OP, unnecessarily. (In my opinion.) The output in circuit 2 will follow \$V_4\$ whether it has, or does not have, a DC offset. Which is, in fact, part of the point. \$\endgroup\$ – jonk Feb 4 '17 at 17:53
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The signal generator is like a battery for A.C. It puts out a sine wave centered at zero volts. In your middle circuit, the signal generator is essentially a dead DC short across R4, and all the current through R3 is flowing through the generator.

Putting a capacitor in series with the signal generator output blocks the DC path through the generator. The generator side of the capacitor is at zero volts DC, along with the +/- AC signal. The other side of the capacitor is at the voltage set by the divider (+6V), along with the AC signal.

The key factor here is that the signal generator has an average output voltage of zero.

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