I'm designing a pcb with an Altera MAX10 (10M02) CPLD used to do, amongst other things, bus arbitration between several memory chips (one /CS per chip). All the memory chip are on same bus so only one /CS (and /OE) shall be toggled low at same time to avoid bus conflict.
To my understanding, the MAX10 CPLD can initialize itself within 2ms at power on (based on uncompressed, un-encrypted binary, numbers I found in a datasheet).
I wanted to know what is the state of the I/O when CPLD is initializing. Are they HighZ? Low? High? Or is the state unpredictable? Some more notes:
- I use verilog "assign" to set all the critical I/O's to 1 by default (assuming registers are 0 after initialisation). Eg: "assign outputname= registername?1'b0 : 1'b1;"
- I've set all the I/O's to 3.3LVCMOS because everything is interfaced with 3.3V devices.
- The rise/fall timing requires to be less than 10ns.
Also, can someone confirm the MAX10 (10M02) CPLD has all registers cleared after initialisation? (I don't use any reset pin). I can't find any details about that on the datasheets.
Thanks for your answer / suggestions.