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I made a custom footprint for an SMD connector I'm using. I wanted to build vias into the footprint for each pad and to connect a trace from each pad to its via. The reason I want to do this is so that I don't need to re-do that routing effort in every component that I place (there are a bunch), and since I know I want to route the signals from the connector on a buried layer. The footprint looks like this:

enter image description here

When I defined the device that uses the footprint, I simply did not "connect" the SMD pads and associated the schematic signal pins with the aforementioned vias.

I made the library part without a problem, but now that I'm going to use it, I am getting lots and lots of DRC errors. These are all related to Clearance between vias, traces, and SMD pads in the library component, and Overlap between my vias and pads and the library traces, without even routing anything. Furthermore, when I actually do route a signal to one of the vias by way of the SMD pad, I get Overlap errors where my trace runs through the SMD pad to get to the library connected via, as shown in the following snippet:

enter image description here

As you can see, I've "approved" 720 DRC errors in my layout that are associated only with the bare library parts. So my question is, how do I define my library part correctly so as to avoid these fictional DRC errors?

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  • \$\begingroup\$ It turns out that Eagle V6 still has this limitation. It frustrated me recently. \$\endgroup\$ – abey Jun 4 '13 at 4:08
  • \$\begingroup\$ Even version 8.4 still has this issue. \$\endgroup\$ – RubenDefour Dec 11 '17 at 10:16
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Yup, that's a issue with Eagle, at least as of version 5. It would be nice if you could tell the DRC check to ignore anything resulting from stuff wholly inside a package, but you can't. There has been talk of changing that, but I don't know where that is at with regard to version 6. It doesn't matter anyway since version 6 isn't ready for any real use yet for a while.

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  • \$\begingroup\$ that's what I figured, I'll give others an opportunity to respond for a couple days before I accept your answer, thanks! \$\endgroup\$ – vicatcu Mar 21 '12 at 13:48
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In fact in cases such as this (where you have multiple pads connected), there is a straight forward way in Eagle V5 and newer to accomplish this.

Below is an example footprint in which there are two SMD pins, each broken out to a hole. The pins and holes are connected using wires. You can also use polygons too, though rectangles and circles cannot be used.

Library footprint with 2 pins broken out to 2 holes

Now the important thing is how we wire them up. Firstly the symbol has two pins, one for each of the two nets. The following connection assignments are made in the device:

Assignments in device

Notice how we assign both the SMD pad and the hole it is connected to on to the same net by using the "append" button in the connection screen. You will see a little connected symbol (circled). If you click on that symbol it will toggle between two symbols (all and any). The latter symbol means that in the layout you can connect to any pin to complete the net, the former means you have to connect to all pins. By selecting the any pin option you won't have to route the traces between the connected pins in the layout.

Once set up this way, when you run DRC on the layout, you don't get any overlap errors. This is because the wires and polygons within the footprint will assign themselves to the of a pin they overlap or intersect with.

No DRC Errors

Above I put two of the parts in the same layout and no DRC issues.

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