I can probably rattle off the design of a full adder off the top of my head, as a network of gates. And given a few minutes, I can probably give circuit diagrams for all the gates involved.

But is this really how building blocks of larger designs are put together? As a programmer, I spend most of my time in a high-level language, but I've been known to drop down to assembly for tight inner loops, simply because the abstractions cost a little bit of efficiency and in some areas every cycle counts.

So similarly, I could imagine a situation where an adder would be designed not out of discrete and separable gates, but as a more complex amalgamation of individual transistors, to improve power consumption/latency/whatever.

Is it potentially worthwhile, and is it done in practice, to design modules such as adders on a transistor level, or is everything just gates?

  • \$\begingroup\$ For the most part, everything is done in a hardware description language (verilog or vhdl), not at the gate level. These languages allow modular and hierarchical design. During synthesis, which is an automated step, optimizations would be used to eliminate logic which serves no purpose. I believe this is easier to detect in hardware than software (compilers do their best, but sometimes leave unused code). I would not be surprised if some parts of a hardware design are sometimes tweaked manually to help meet timing or something. But in a large design, there are an awful lot of transistors. \$\endgroup\$
    – user57037
    Commented Feb 4, 2017 at 19:05
  • 2
    \$\begingroup\$ In ASICs, the question even reaches down to the level of production masks. As feature sizes have shrunk, the masks no longer look much like the resulting mask on wafer because of optical diffraction. There's an algorithm to tweak the masks themselves so they produce the right thing in the end and that algorithm is highly specific to the fab and process. But if a "concept" is important enough and/or used often enough, it's always possible to teach the compiler to recognize it and to apply a canned approach at an appropriate level of abstraction or concreteness. Same thing designing electronics. \$\endgroup\$
    – jonk
    Commented Feb 4, 2017 at 19:15
  • \$\begingroup\$ Cost benefit analyses are king. Its not often that shaving a transistor off of a circuit is worth the time it took to model it that way. However, I do remember a particular cache from the DEC Alpha which was unclocked. It relies on knowing the exact propagation delays through the transistors to make sure the data came out at the right time. Made it really fast... and scaled poorly. Within a few years, the more traditional caches were dominating over it. \$\endgroup\$
    – Cort Ammon
    Commented May 23, 2017 at 7:03
  • \$\begingroup\$ To answer your question simply, yes, it all boils down to transistors. MOSFETS, specifically. Using discrete transistors is not necessarily more efficient than pre-fabricated IC's, and would probably be more costly, too. \$\endgroup\$ Commented Aug 22, 2017 at 19:22

2 Answers 2


Absolutely. If you're doing high performance, full custom chip design, anything to get an edge will be done, including transistor level design of critical blocks. However, even at a standard cell library level, things like adders are implemented using more complex blocks than simple AND and OR gates. A full adder can be built out of a more specialized collection of transistors than what would directly correspond to the equivalent logic gates. A standard cell library will include several variations of full and half adder cells alongside the more basic AND, OR, NOT, XOR, etc. gates, as well as some common combinations such as and-or-invert (AOI) and similar that are relatively common and can be built more efficiently at a transistor level. Same goes for latches and flip flops. You won't use a pair of cross connected gates for a latch, you would use a specially designed latch cell.


I've friends, very strong in Verilog and VHDL, who tell me about various optimization switches: fastest, lowest area, lowest power, etc. The Synthesizer tool may have differently crafted gates, perhaps the same topology but with different transistors, for different purposes.

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    \$\begingroup\$ It's 'synthesis' tools...synthesizer tools are for creating 12-minute Emerson Lake and Palmer solos \$\endgroup\$
    – TonyM
    Commented Jul 23, 2017 at 9:00

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