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I'm new to EE and have a question about signal buffering. I'd like to use two brief paragraphs to give some background and context.

I live in the SE Asian country-side. Mains supply (230VAC 50Hz) is unreliable and noisy: voltage occasionally drifts down to 200V and contains transients from old irrigation pump relay switches, and who-knows what else. In response to frequent power outages anyone with a desktop PC also has a UPS but many people report that their UPS simply dies after 6 months. I've had a cheap one burst into flames after it switched rapidly under low mains supply.

To provide my electronic equipment with "cleaner" and steady power, I am designing a power regulator that transforms mains AC down to 36V rectified DC and then regulates its voltage and current to 24V and 16A. My question relates to the circuit that indicates the output voltage of the transformer/rectifier stage.

My design emulates the LM3914 LED bar display: receive the signal, shape and buffer it, then pass it off to a resistor ladder with an op-amp array driving the LED display bar. The signal buffer sub-circuit is shown below. It uses an op-amp clamp circuit outlined on wikipedia, with a 5V reference clamping voltage, and a negative (2.5V) clipper on the output.

Signal input buffer circuit

The signal comes in hot from the transformer just after having been rectified to DC. At 230VAC the transformer should yield 36VAC but due to the gruesome state of the mains supply it could drift down to 26VAC several times during the day, as well as spike to 60VAC on transients. So, although expected to be a nominal 36V, the DC input ranges between 0-60V and I want to visually monitor its variance. The circuit above immediately divides the signal down to 0-11V range (at node W) and a zener diode clips spikes above 8.2V. The signal is then below the 12V supply to the op-amp.

Signal plots

The test signal (top panel), during phase B simulates a few transients and then rises to 50V after which it drops to zero (power outage) at phase C. Since most of the input signal variance is expected to be between 24V and 40V, I am only interested in buffering this range (between the red arrow heads, 24-40V). Hence, the clamping op-amp configuration. To get rid of signal <0V a clipper via D3 removes the lower 2.5V of the op-amp output signal (lower panel).

The buffer can then provide the interesting mid-band of signal to the LED display circuit as a tight and efficient 0-5V representation of the 24-40V range of the wild transformer output.

However, during phase A (start-up) and after phase C (power outage) the op-amp output tends toward the 5V reference voltage. How can this be avoided? When input is zero, the buffer output should, truthfully, tend to its minimum too.

In addition to the main question, I would appreciate comments about the circuit design and choice of components and welcome advice for handling phase A (soft start?) and correcting input/output impedance.

Update

Using @The Photon's advice I went back to reading about clipping and clamping today. The input signal is not AC and almost all of the attempts to clip and clamp in my original circuit diagram (above) were misguided.

Updated signal buffer

So, as suggested in the accepted answer, I got rid of the capacitor, voltage reference, etc and replaced everything with a zener diode, D2, which offsets the pre-opamp DC signal (yellow plot in the image below) downwards into the 0-5V range I require at buffer output (green plot)

Also suggested in the answer: increase the values of R1 and R2 and reduce strain on op-amp. Circuit current is down to micro Amps. The most active component, the op-amp output, is plotted in grey.

signal plots after update

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  • \$\begingroup\$ Most ATX type SMPS only have enough storage capacity for 1 cycle dropout at rated power. If you need 2,3,4 or more cycle storage capacity for transient outage then more capacity is required so that you only use 50%,25% or less of the rated capacity. Otherwise UPS battery back up the preferred solution for either DC-DC or DC-AC reliable outputs. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Feb 4 '17 at 20:10
  • \$\begingroup\$ @TonyStewart.EEsince'75, the AC voltage around here regularly dips into the range where consumer grade UPSes switch to battery output, then sense current from the mains, switch back and eventually just start thrashing between states. Great info about increasing capacity for ATX supplies. \$\endgroup\$ – venzen Feb 5 '17 at 17:23
  • \$\begingroup\$ the preferred approach in your situation may be the type of UPS which is always in use on float charge then it won't cut-out until the A-h capacity is drained. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Feb 5 '17 at 17:45
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My comments

  1. If "SIG" is the output of a full rectifier, then capacitor C1 is going to drop the DC component before it reaches your clamp circuit. You're going to have a signal at bufferOUT that is varying above and below ground. Exactly how much above and below depends on the exact shape of the waveform at SIG.

    This is also what's causing your output to trend back toward 5 V when the SIG input stays constant for a long time.

  2. 60 V input and 4 kohms at R1 implies you're working with 10's of mA of current. The op-amp will have to sink all of this current when it works as a clamp. The LM324 is only guaranteed to sink about 10 mA. Typically it should do 20 mA, but no promises.

    You can reduce the need of the op-amp to sink large currents by replacing D2 with the b-e junction of a pnp transistor, and tying the collector to ground.

  3. This clamp circuit depends on the op-amp being able to switch between saturated and active operation quickly. Most modern op-amps aren't good at this, though I don't know about the '324 specifically.

Why not just use a 5 V zener and be done with it?

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  • \$\begingroup\$ What he wants to do is convert the 24 to 40 volt range to 0 to 5 volts, with excursions outside this band clipped to 0 and 5. So no, a simple 5V zener won't really do. \$\endgroup\$ – WhatRoughBeast Feb 4 '17 at 20:01
  • \$\begingroup\$ Thanks, @The Photon. I was looking for fish up a tree. A single zener diode did the trick, as illustrated in an update to my question. Not sure if that was your actual suggestion, but I haven't seen one other similar example of using a zener with an opamp to offset DC in the 20 articles i read on the topic during the past 3 days! Thanks also for the advice about reducing current. \$\endgroup\$ – venzen Feb 5 '17 at 16:55
  • \$\begingroup\$ And you were very right about the behavior of the op-amp. Wherever the signal spikes (even though clipped) came too close to its supply voltage, it would ramp up to 40mA trying to reduce it. So, tweaking the bdvs of the clipping and offset zeners eventually found the sweetspot, hence the 4.7V zener instead of 5V. \$\endgroup\$ – venzen Feb 5 '17 at 17:12
  • \$\begingroup\$ @WhatRoughBeast, who would have thought? a single zener in the op-amp feedback loop does, in fact, perform the voltage offset. \$\endgroup\$ – venzen Feb 5 '17 at 17:16
  • \$\begingroup\$ @venzen, one thing to watch out for in your design: There's two solutions, with the zener either reverse biased (the one you want), or forward biased (giving an offset of +0.6 V instead of -4.7). You can probably select the one you want by connecting the op-amp inverting input to the high voltage rail with a reasonable resistor (10k?). \$\endgroup\$ – The Photon Feb 5 '17 at 17:21

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