It's been a while since I've looked at the recent Microchip processors & I've been trying to learn a little bit about the PIC32 MIPS instruction set. I noticed there are two sets of branch instructions; the programming guide says this:
184.108.40.206 Branch Delays and the Branch Delay Slot
All branches have an architectural delay of one instruction. The instruction immediately following a branch is said to be in the branch delay slot. If a branch or jump instruction is placed in the branch delay slot, the operation of both instructions is undefined.
By convention, if an exception or interrupt prevents the completion of an instruction in the branch delay slot, the instruction stream is continued by re-executing the branch instruction. To permit this, branches must be restartable; procedure calls may not use the register in which the return link is stored (usually GPR 31) to determine the branch target address.
220.127.116.11 Branch and Branch Likely
Branch instructions execute the instruction in the delay slot.
Branch likely instructions do not execute the instruction in the delay slot if the branch is not taken (they are said to nullify the instruction in the delay slot).
Although the Branch Likely instructions are included in this specification, software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Could someone clarify what they're saying here? Do they differ in the # of CPU cycles taken in each case?
I'm used to the branching architectures of the 8- and 16-bit PICs ("branch skip") where you either execute or jump over an instruction (this sounds like Branch Likely), and I'm used to the branching architecture of the TI C2000 DSPs (where all you get is a branch or branch conditional to an address). But I don't quite understand how to map the MIPS branch instructions onto my existing knowledge.