I understand that thee voltage level for LVDS standard has a typical offset voltage of 1.25V and voltage swing of 350mV. However, when I am doing some pin mapping on Xilinx FPGA, I encountered some different LVDS standard: LVDS_25, LVDS_18 etc...

May I know what is the voltage range for LVDS_25? Does that mean offset of 2.5V and voltage swing of 350mV?where for positive output of (2.5+0.35)V is a logic '1' and (2.5-0.35)V is a logic '0' and vice versa for complementary output port?

Thank you

  • \$\begingroup\$ I am thinking that LVDS_25 is LVDS for 2.5V systems. So the center point is 1.25V. Similarly, LVDS_18 is LVDS for 1.8V systems, and the center point is 0.9V. This is just a guess. \$\endgroup\$
    – user57037
    Commented Feb 5, 2017 at 2:35
  • \$\begingroup\$ Thank you. Anyway, I will keep here posted if I found any trusted source. \$\endgroup\$
    – user9870
    Commented Feb 5, 2017 at 3:15
  • 1
    \$\begingroup\$ LVDC_18 uses 1.8V, LVDC_25 uses 2.5V and LVDC_33 uses 3.3V for Vcc(Aux) \$\endgroup\$ Commented Feb 5, 2017 at 3:48
  • 7
    \$\begingroup\$ LVDS_25 means that the IO banks use (or rather expect) a supply voltage of 2.5V as an LVDS_18 IO pin expect a supply voltage of 1.8V. The common mode voltage (or offset voltage) is usually half the supply voltage. the 350mV is teh differential swing between the LVDS pair. E.g. say you were using LVDS25, that's an offset voltage of 1.25V and with a differential swing of 350mV that means that one wire would go to 2.5/2 + 0.35/2 Volts while the other would swing to 2.5/2 - 0.35/2 volts. The receiver is really just a comparator so the exact offset voltage and swing isn't usually too critical. \$\endgroup\$
    – Sam
    Commented Feb 5, 2017 at 7:30
  • 2
    \$\begingroup\$ Thank you Sam.. This make things so clear, can you please transfer your answer to answer section so I can mark as answer \$\endgroup\$
    – user9870
    Commented Feb 5, 2017 at 15:05

1 Answer 1


LVDS_XX only gives you the voltage of the power rail for that IO bank. LVDS_25 is only allowed on a 2.5V bank, LVDS_18 is only allowed on a 1.8V bank, etc. The actual voltage levels are just "LVDS level."

The information in this Answer specifically targets Xilinx, because that's what the question refers to and that's what I'm experienced with. To apply this to other FPGAs or devices, just check the input and output specs on the datasheet.

LVDS common mode voltage is around 1.25V. See the blue circles in the below tables.
LVDS differential voltage is around 350mV. See the red circles in the below tables.

To know if a driver is compatible with a given receiver, check the levels. If the output min is above the input min, and the output max is below the input max, you're fine. Check the whole datasheet for other constraints, such as max IO-to-Vsupply difference (the Xilinx datasheet takes this into account).

Xilinx LVDS_25 Levels source

Xilinx LVDS_18 Levels source
NOTE: "LVDS" here is referred to as "LVDS_18" in other contexts.

Information and tables taken from the following sources:


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