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lately i was analyzing a simple circuit with 2 MOSFET, 1 Nmos and 1 Pmos, where the Nmos was acting as a switch and its drain was connected through a resistance to the Pmos' gate. The pmos had it's source connected to a positive reference voltage and it's drain connected to a load. Between the Pmos' gate and drain a capacitor was placed. Now, i was trying to get the circuit polarization but to me, when no signal is applied to the Nmos' gate, the Pmos should have its gate floating. But in reality it seems that that Pmos should actually be turned off and not on.

Am i not considering some aspects of a 'real-life' MOSFET for this? Thanks in advance.

EDIT - Here's the schematic:

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  • \$\begingroup\$ add the circuit diagram, to get more answers \$\endgroup\$
    – Raj
    Feb 5, 2017 at 9:48
  • \$\begingroup\$ "But in reality it seems that that Pmos should actually be turned off and not off." Its not clear what you are asking.. Posting schematic of the circuit can help you in getting some answers.. \$\endgroup\$
    – nidhin
    Feb 5, 2017 at 9:51
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    \$\begingroup\$ In stead of coming up with "your own" circuit ideas on how to use a PMOS, I most strongly advise you to look at working designs and design examples which show how to use a PMOS (or NMOS). Exercises like you have here are only going to confuse you more and will not teach you how a PMOS should be used. It will only add to more confusion and you'll never learn how to propely use a PMOS. Transistors are complex devices, others have figured out how to use them, learn from that. \$\endgroup\$ Feb 5, 2017 at 11:09

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What is likely to happen is that you create a latch. The n channel fet turns on and charges the capacitor. This activates the P channel fet. If the n channel is turned off, the cap remains charged and the P channel fet remains activated.

However, over time, the cap may slowly discharge and the P channel fet will gradually turn off. There is no other mechanism in your circuit for turning the P channel fet off. Basically, as it stands, I would describe it as a flawed circuit.

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The circuit appears 'sub-optimum' unless you desire some very unusual functionality. Explaining what the circuit is intended to achieve would help heaps.

If Vsignal is initially low, then when Vcc is first applied the voltage on C1 will be 0 so the gate of M1 will be loaded to ground by "load".
M1 will see a gate voltage of Vcc divided by C1 and Cgs of M1. This will in most cases turn M1 on.
There is no significant discharge path for C1 (mainly M2 ds leakage) so if C1 leakage is low, as it typically will be for a non polarised capacitor), M1 will tend to stay on.

Turning M2 on will formally turn M1 on and when M2 is turned off M1 will remain on as above.

To have M1 turn off when M2 is off a resistor R2 can be added to M1gs.

  • This will divide M2 drive signal by a factor of R2/(R1+R2) so needs to be sufficiently large to avoid unintended effects.

  • When M2 is turned off M1 will remain on due to C1 being charged. C1 will discharge via R2 with time constant R2C1. The time constant should be low enough to avoided undesired consequences while noting the need in the prior paragraph.

  • RC turnoff of M1 will result in a slow turnoff and the FET will dissipate power as it transits from on to off. Depending on the component values this may be harmless or may destroy the FET.

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When the n-FET is turned on, the p-FET gate is pulled low and C1 is charged up.

When the n-FET is turned off, C1 charge (as well as the p-FET gate charge) keeps the p-FET on, at least at first.

What will happen over time isn't as clear:

  • C1 charge leaks away. Vgs eventually gets to sub-threshold, drain voltage starts to go down, gate will follow it slowly. (Model this with a high resistance across the capacitor.)

  • (more likely) n-FET has some leakage, at least more than C1's, keeping C1 and the p-FET gate charged. So it stays on and can never be turned off. Check the FET model for its off-state leakage spec.

Besides being unpredictable, this circuit is vulnerable to noise pickup. Not good...

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